Commit 3ac72e98 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/gr/gf100-: virtualise init_ds_hww_esr_2 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 2585a1b1

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

+2 −0
Original line number Diff line number Diff line
@@ -2018,6 +2018,8 @@ gf100_gr_init(struct gf100_gr *gr) 
	nvkm_wr32(device, 0x400124, 0x00000002);



	gr->func->init_fecs_exceptions(gr);

	if (gr->func->init_ds_hww_esr_2)

		gr->func->init_ds_hww_esr_2(gr);



	nvkm_wr32(device, 0x404000, 0xc0000000);

	nvkm_wr32(device, 0x404600, 0xc0000000);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h

+2 −0
Original line number Diff line number Diff line
@@ -131,6 +131,7 @@ struct gf100_gr_func { 
	void (*init_bios_2)(struct gf100_gr *);

	void (*init_swdx_pes_mask)(struct gf100_gr *);

	void (*init_fecs_exceptions)(struct gf100_gr *);

	void (*init_ds_hww_esr_2)(struct gf100_gr *);

	void (*init_ppc_exceptions)(struct gf100_gr *);

	void (*set_hww_esr_report_mask)(struct gf100_gr *);

	const struct gf100_gr_pack *mmio;
@@ -165,6 +166,7 @@ int gk20a_gr_init(struct gf100_gr *); 


int gm200_gr_rops(struct gf100_gr *);

void gm200_gr_init_num_active_ltcs(struct gf100_gr *);

void gm200_gr_init_ds_hww_esr_2(struct gf100_gr *);



int gp100_gr_init(struct gf100_gr *);

void gp100_gr_init_rop_active_fbps(struct gf100_gr *);

drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c

+10 −2
Original line number Diff line number Diff line
@@ -38,6 +38,14 @@ gm200_gr_rops(struct gf100_gr *gr) 
	return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c);

}



void

gm200_gr_init_ds_hww_esr_2(struct gf100_gr *gr)

{

	struct nvkm_device *device = gr->base.engine.subdev.device;

	nvkm_wr32(device, 0x405848, 0xc0000000);

	nvkm_mask(device, 0x40584c, 0x00000001, 0x00000001);

}



void

gm200_gr_init_num_active_ltcs(struct gf100_gr *gr)

{
@@ -92,8 +100,7 @@ gm200_gr_init(struct gf100_gr *gr) 
	nvkm_wr32(device, 0x40013c, 0xffffffff);

	nvkm_wr32(device, 0x400124, 0x00000002);

	gr->func->init_fecs_exceptions(gr);

	nvkm_wr32(device, 0x405848, 0xc0000000);

	nvkm_wr32(device, 0x40584c, 0x00000001);

	gr->func->init_ds_hww_esr_2(gr);

	nvkm_wr32(device, 0x404000, 0xc0000000);

	nvkm_wr32(device, 0x404600, 0xc0000000);

	nvkm_wr32(device, 0x408030, 0xc0000000);
@@ -194,6 +201,7 @@ gm200_gr = { 
	.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,

	.init_rop_active_fbps = gm200_gr_init_rop_active_fbps,

	.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,

	.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,

	.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,

	.rops = gm200_gr_rops,

	.ppc_nr = 2,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c

+2 −2
Original line number Diff line number Diff line
@@ -70,8 +70,7 @@ gp100_gr_init(struct gf100_gr *gr) 
	nvkm_wr32(device, 0x40013c, 0xffffffff);

	nvkm_wr32(device, 0x400124, 0x00000002);

	gr->func->init_fecs_exceptions(gr);

	nvkm_wr32(device, 0x405848, 0xc0000000);

	nvkm_mask(device, 0x40584c, 0x00000000, 0x00000001);

	gr->func->init_ds_hww_esr_2(gr);

	nvkm_wr32(device, 0x404000, 0xc0000000);

	nvkm_wr32(device, 0x404600, 0xc0000000);

	nvkm_wr32(device, 0x408030, 0xc0000000);
@@ -134,6 +133,7 @@ gp100_gr = { 
	.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,

	.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,

	.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,

	.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,

	.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,

	.rops = gm200_gr_rops,

	.ppc_nr = 2,

drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c

+1 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ gp102_gr = { 
	.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,

	.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,

	.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,

	.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,

	.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,

	.rops = gm200_gr_rops,

	.ppc_nr = 3,