Commit 3b1a57c4 authored by Nathan Lu's avatar Nathan Lu Committed by Matthias Brugger
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soc: mediatek: add mtk-mmsys support for mt8188 vdosys0 



1. add mt8188 mmsys
2. add mt8188 vdosys0 routing table settings

Signed-off-by: default avataramy zhang <Amy.Zhang@mediatek.com>
Signed-off-by: default avatarNathan Lu <nathan.lu@mediatek.com>
Link: https://lore.kernel.org/r/20221206020046.11333-5-nathan.lu@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 5d98c635

drivers/soc/mediatek/mt8188-mmsys.h

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+149 −0
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/* SPDX-License-Identifier: GPL-2.0-only */



#ifndef __SOC_MEDIATEK_MT8188_MMSYS_H

#define __SOC_MEDIATEK_MT8188_MMSYS_H



#define MT8188_VDO0_OVL_MOUT_EN				0xf14

#define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0		BIT(0)

#define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0		BIT(1)

#define MT8188_MOUT_DISP_OVL0_TO_DISP_OVL1		BIT(2)

#define MT8188_MOUT_DISP_OVL1_TO_DISP_RDMA1		BIT(4)

#define MT8188_MOUT_DISP_OVL1_TO_DISP_WDMA1		BIT(5)

#define MT8188_MOUT_DISP_OVL1_TO_DISP_OVL0		BIT(6)



#define MT8188_VDO0_SEL_IN				0xf34

#define MT8188_VDO0_SEL_OUT				0xf38



#define MT8188_VDO0_DISP_RDMA_SEL			0xf40

#define MT8188_SOUT_DISP_RDMA0_TO_MASK			GENMASK(2, 0)

#define MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0		(0 << 0)

#define MT8188_SOUT_DISP_RDMA0_TO_DISP_DSI0		(1 << 0)

#define MT8188_SOUT_DISP_RDMA0_TO_DISP_DP_INTF0		(5 << 0)

#define MT8188_SEL_IN_DISP_RDMA0_FROM_MASK		GENMASK(8, 8)

#define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0		(0 << 8)

#define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_RSZ0		(1 << 8)





#define MT8188_VDO0_DSI0_SEL_IN				0xf44

#define MT8188_SEL_IN_DSI0_FROM_MASK			BIT(0)

#define MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT		(0 << 0)

#define MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0		(1 << 0)



#define MT8188_VDO0_DP_INTF0_SEL_IN			0xf4C

#define MT8188_SEL_IN_DP_INTF0_FROM_MASK		GENMASK(2, 0)

#define MT8188_SEL_IN_DP_INTF0_FROM_DSC_WRAP0C1_OUT	(0 << 0)

#define MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE		(1 << 0)

#define MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0	(3 << 0)



#define MT8188_VDO0_DISP_DITHER0_SEL_OUT		0xf58

#define MT8188_SOUT_DISP_DITHER0_TO_MASK		GENMASK(2, 0)

#define MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN	(0 << 0)

#define MT8188_SOUT_DISP_DITHER0_TO_DSI0		(1 << 0)

#define MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0		(6 << 0)

#define MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0		(7 << 0)



#define MT8188_VDO0_VPP_MERGE_SEL			0xf60

#define MT8188_SEL_IN_VPP_MERGE_FROM_MASK		GENMASK(1, 0)

#define MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT	(0 << 0)

#define MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT	(3 << 0)



#define MT8188_SOUT_VPP_MERGE_TO_MASK			GENMASK(6, 4)

#define MT8188_SOUT_VPP_MERGE_TO_DSI1			(0 << 4)

#define MT8188_SOUT_VPP_MERGE_TO_DP_INTF0		(1 << 4)

#define MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0		(2 << 4)

#define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA1		(3 << 4)

#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN		(4 << 4)

#define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0		(5 << 4)

#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK	GENMASK(11, 11)

#define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN		(0 << 11)



#define MT8188_VDO0_DSC_WARP_SEL			0xf64

#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK		GENMASK(0, 0)

#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0	(0 << 0)

#define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_VPP_MERGE	(1 << 0)

#define MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK		GENMASK(19, 16)

#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0		BIT(16)

#define MT8188_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0	BIT(17)

#define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE		BIT(18)

#define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0		BIT(19)



static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {

	{

		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,

		MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0,

		MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0

	}, {

		DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,

		MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0,

		MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0

	}, {

		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,

		MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK,

		MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0

	}, {

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,

		MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,

		MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0

	}, {

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_MERGE0,

		MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,

		MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT

	}, {

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,

		MT8188_VDO0_DSC_WARP_SEL,

		MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK,

		MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0

	}, {

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0,

		MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK,

		MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,

		MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,

		MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,

		MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,

		MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT

	}, {

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,

		MT8188_VDO0_DISP_RDMA_SEL, MT8188_SOUT_DISP_RDMA0_TO_MASK,

		MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0

	},  {

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,

		MT8188_VDO0_DISP_DITHER0_SEL_OUT,

		MT8188_SOUT_DISP_DITHER0_TO_MASK,

		MT8188_SOUT_DISP_DITHER0_TO_DSI0

	},  {

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0,

		MT8188_VDO0_DISP_DITHER0_SEL_OUT,

		MT8188_SOUT_DISP_DITHER0_TO_MASK,

		MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,

		MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,

		MT8188_SOUT_VPP_MERGE_TO_DP_INTF0

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,

		MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,

		MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA0,

		MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,

		MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,

		MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,

		MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,

		MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,

		MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,

		MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,

		MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE

	},

};



#endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */

drivers/soc/mediatek/mtk-mmsys.c

+11 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include "mt8167-mmsys.h"

#include "mt8183-mmsys.h"

#include "mt8186-mmsys.h"

#include "mt8188-mmsys.h"

#include "mt8192-mmsys.h"

#include "mt8195-mmsys.h"

#include "mt8365-mmsys.h"
@@ -67,6 +68,12 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 
	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,

};



static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {

	.clk_driver = "clk-mt8188-vdo0",

	.routes = mmsys_mt8188_routing_table,

	.num_routes = ARRAY_SIZE(mmsys_mt8188_routing_table),

};



static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {

	.clk_driver = "clk-mt8192-mm",

	.routes = mmsys_mt8192_routing_table,
@@ -299,6 +306,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { 
		.compatible = "mediatek,mt8186-mmsys",

		.data = &mt8186_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8188-vdosys0",

		.data = &mt8188_vdosys0_driver_data,

	},

	{

		.compatible = "mediatek,mt8192-mmsys",

		.data = &mt8192_mmsys_driver_data,