Commit 3b2b69ef authored by David S. Miller's avatar David S. Miller
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net 



Mainline had UFO fixes, but UFO is removed in net-next so we
take the HEAD hunks.

Minor context conflict in bcmsysport statistics bug fix.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 2e2d5d76 26273939

Documentation/gpio/gpio-legacy.txt

+1 −1
Original line number Original line Diff line number Diff line
@@ -459,7 +459,7 @@ pin controller? 




This is done by registering "ranges" of pins, which are essentially

This is done by registering "ranges" of pins, which are essentially

cross-reference tables. These are described in

cross-reference tables. These are described in

Documentation/pinctrl.txt

Documentation/driver-api/pinctl.rst





While the pin allocation is totally managed by the pinctrl subsystem,

While the pin allocation is totally managed by the pinctrl subsystem,

gpio (under gpiolib) is still maintained by gpio drivers. It may happen

gpio (under gpiolib) is still maintained by gpio drivers. It may happen

MAINTAINERS

+1 −1
Original line number Original line Diff line number Diff line
@@ -10395,7 +10395,7 @@ L: linux-gpio@vger.kernel.org 
T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git

S:	Maintained

S:	Maintained

F:	Documentation/devicetree/bindings/pinctrl/

F:	Documentation/devicetree/bindings/pinctrl/

F:	Documentation/pinctrl.txt

F:	Documentation/driver-api/pinctl.rst

F:	drivers/pinctrl/

F:	drivers/pinctrl/

F:	include/linux/pinctrl/

F:	include/linux/pinctrl/

arch/sparc/include/asm/spitfire.h

+16 −0
Original line number Original line Diff line number Diff line
@@ -47,10 +47,26 @@ 
#define SUN4V_CHIP_NIAGARA5	0x05

#define SUN4V_CHIP_NIAGARA5	0x05

#define SUN4V_CHIP_SPARC_M6	0x06

#define SUN4V_CHIP_SPARC_M6	0x06

#define SUN4V_CHIP_SPARC_M7	0x07

#define SUN4V_CHIP_SPARC_M7	0x07

#define SUN4V_CHIP_SPARC_M8	0x08

#define SUN4V_CHIP_SPARC64X	0x8a

#define SUN4V_CHIP_SPARC64X	0x8a

#define SUN4V_CHIP_SPARC_SN	0x8b

#define SUN4V_CHIP_SPARC_SN	0x8b

#define SUN4V_CHIP_UNKNOWN	0xff

#define SUN4V_CHIP_UNKNOWN	0xff





/*

 * The following CPU_ID_xxx constants are used

 * to identify the CPU type in the setup phase

 * (see head_64.S)

 */

#define CPU_ID_NIAGARA1		('1')

#define CPU_ID_NIAGARA2		('2')

#define CPU_ID_NIAGARA3		('3')

#define CPU_ID_NIAGARA4		('4')

#define CPU_ID_NIAGARA5		('5')

#define CPU_ID_M6		('6')

#define CPU_ID_M7		('7')

#define CPU_ID_M8		('8')

#define CPU_ID_SONOMA1		('N')



#ifndef __ASSEMBLY__

#ifndef __ASSEMBLY__





enum ultra_tlb_layout {

enum ultra_tlb_layout {

arch/sparc/kernel/cpu.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -506,6 +506,12 @@ static void __init sun4v_cpu_probe(void) 
		sparc_pmu_type = "sparc-m7";

		sparc_pmu_type = "sparc-m7";

		break;

		break;





	case SUN4V_CHIP_SPARC_M8:

		sparc_cpu_type = "SPARC-M8";

		sparc_fpu_type = "SPARC-M8 integrated FPU";

		sparc_pmu_type = "sparc-m8";

		break;



	case SUN4V_CHIP_SPARC_SN:

	case SUN4V_CHIP_SPARC_SN:

		sparc_cpu_type = "SPARC-SN";

		sparc_cpu_type = "SPARC-SN";

		sparc_fpu_type = "SPARC-SN integrated FPU";

		sparc_fpu_type = "SPARC-SN integrated FPU";

arch/sparc/kernel/cpumap.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -328,6 +328,7 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index) 
	case SUN4V_CHIP_NIAGARA5:

	case SUN4V_CHIP_NIAGARA5:

	case SUN4V_CHIP_SPARC_M6:

	case SUN4V_CHIP_SPARC_M6:

	case SUN4V_CHIP_SPARC_M7:

	case SUN4V_CHIP_SPARC_M7:

	case SUN4V_CHIP_SPARC_M8:

	case SUN4V_CHIP_SPARC_SN:

	case SUN4V_CHIP_SPARC_SN:

	case SUN4V_CHIP_SPARC64X:

	case SUN4V_CHIP_SPARC64X:

		rover_inc_table = niagara_iterate_method;

		rover_inc_table = niagara_iterate_method;