Commit 3c033fb1 authored by Marek Vasut's avatar Marek Vasut Committed by Shawn Guo
Browse files

arm64: dts: imx8mm: Deduplicate PCIe clock-names property 



Move the PCIe clock-names property from various DTs into SoC dtsi to
reduce duplication. In case of a couple of boards, reorder the clock
so they match the order in yaml DT bindings.

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mm.dtsi, imx8mm-tqma8mqml-mba8mx.dts
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Reviewed-by: default avatarRichard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 7e5f78c7

arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -241,9 +241,8 @@ &pcie0 { 
	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,

		 <&pcie0_refclk_gated>;

	clock-names = "pcie", "pcie_aux", "pcie_bus";

	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,

		 <&clk IMX8MM_CLK_PCIE1_AUX>;

	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,

			  <&clk IMX8MM_CLK_PCIE1_CTRL>;

	assigned-clock-rates = <10000000>, <250000000>;

arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts

+2 −3
Original line number Diff line number Diff line
@@ -904,9 +904,8 @@ &pcie0 { 
	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,

		 <&pcieclk 0>;

	clock-names = "pcie", "pcie_aux", "pcie_bus";

	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>,

		 <&clk IMX8MM_CLK_PCIE1_AUX>;

	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,

			  <&clk IMX8MM_CLK_PCIE1_CTRL>;

	assigned-clock-rates = <10000000>, <250000000>;

arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -360,9 +360,8 @@ &pcie0 { 
	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,

		 <&pcie0_refclk>;

	clock-names = "pcie", "pcie_aux", "pcie_bus";

	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,

		 <&clk IMX8MM_CLK_PCIE1_AUX>;

	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,

			  <&clk IMX8MM_CLK_PCIE1_CTRL>;

	assigned-clock-rates = <10000000>, <250000000>;

arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi

+0 −3
Original line number Diff line number Diff line
@@ -210,9 +210,6 @@ &pcie0 { 
	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;

	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,

		 <&clk IMX8MM_CLK_PCIE1_AUX>;

	clock-names = "pcie", "pcie_bus", "pcie_aux";

	fsl,max-link-speed = <1>;

	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>;

	assigned-clock-rates = <10000000>, <250000000>;

arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts

+0 −3
Original line number Diff line number Diff line
@@ -175,9 +175,6 @@ &pcie0 { 
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,

				 <&clk IMX8MM_SYS_PLL2_250M>;

	assigned-clock-rates = <10000000>, <250000000>;

	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,

		 <&clk IMX8MM_CLK_PCIE1_PHY>;

	clock-names = "pcie", "pcie_aux", "pcie_bus";

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie>;

	reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;