Commit 3c1fbd51 authored by Mike Frysinger's avatar Mike Frysinger Committed by Bryan Wu
Browse files

Blackfin arch: rewrite blackfin_invalidate_entire_dcache function 



rewrite blackfin_invalidate_entire_dcache() in C for easier management,
better optimization, and so we take all SSYNC anomalies into account

Signed-off-by: default avatarMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent fe85cad2

arch/blackfin/mach-common/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
#



obj-y := \

	cache.o entry.o head.o \

	cache.o cache-c.o entry.o head.o \

	interrupt.o irqpanic.o arch_checks.o ints-priority.o



obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o

arch/blackfin/mach-common/cache-c.c

0 → 100644
+24 −0
Original line number Diff line number Diff line 
/*

 * Blackfin cache control code (simpler control-style functions)

 *

 * Copyright 2004-2008 Analog Devices Inc.

 *

 * Enter bugs at http://blackfin.uclinux.org/

 *

 * Licensed under the GPL-2 or later.

 */



#include <asm/blackfin.h>



/* Invalidate the Entire Data cache by

 * clearing DMC[1:0] bits

 */

void blackfin_invalidate_entire_dcache(void)

{

	u32 dmem = bfin_read_DMEM_CONTROL();

	SSYNC();

	bfin_write_DMEM_CONTROL(dmem & ~0xc);

	SSYNC();

	bfin_write_DMEM_CONTROL(dmem);

	SSYNC();

}

arch/blackfin/mach-common/cache.S

+0 −36
Original line number Diff line number Diff line
@@ -97,39 +97,3 @@ ENTRY(_blackfin_dflush_page) 
	P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);

	jump .Ldfr;

ENDPROC(_blackfin_dflush_page)
 


/* Invalidate the Entire Data cache by

 * clearing DMC[1:0] bits

 */

ENTRY(_blackfin_invalidate_entire_dcache)

	[--SP] = ( R7:5);



	P0.L = LO(DMEM_CONTROL);

	P0.H = HI(DMEM_CONTROL);

	R7 = [P0];

	R5 = R7;	/* Save DMEM_CNTR */



	/* Clear the DMC[1:0] bits, All valid bits in the data

	 * cache are set to the invalid state

	 */

	BITCLR(R7,DMC0_P);

	BITCLR(R7,DMC1_P);

	CLI R6;

	SSYNC;		/* SSYNC required before writing to DMEM_CONTROL. */

	.align 8;

	[P0] = R7;

	SSYNC;

	STI R6;



	/* Configures the data cache again */



	CLI R6;

	SSYNC;		/* SSYNC required before writing to DMEM_CONTROL. */

	.align 8;

	[P0] = R5;

	SSYNC;

	STI R6;



	( R7:5) = [SP++];

	RTS;

ENDPROC(_blackfin_invalidate_entire_dcache)