Commit 3d256330 authored by Han Xu's avatar Han Xu Committed by Shawn Guo
Browse files

arm64: dts: imx8ulp-evk: add spi-nor device support 



Add spi-nor support.
- 8 bit mode for RX/TX.
- Set the clock rate to 200MHz.
- add default/sleep pinctrl.

Co-developed-by: default avatarHaibo Chen <haibo.chen@nxp.com>
Signed-off-by: default avatarHaibo Chen <haibo.chen@nxp.com>
Signed-off-by: default avatarHan Xu <han.xu@nxp.com>
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 014fbffa

arch/arm64/boot/dts/freescale/imx8ulp-evk.dts

+32 −0
Original line number Diff line number Diff line
@@ -95,6 +95,21 @@ &cm33 { 
	status = "okay";

};



&flexspi2 {

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&pinctrl_flexspi2_ptd>;

	pinctrl-1 = <&pinctrl_flexspi2_ptd>;

	status = "okay";



	mx25uw51345gxdi00: flash@0 {

		compatible = "jedec,spi-nor";

		reg = <0>;

		spi-max-frequency = <200000000>;

		spi-tx-bus-width = <8>;

		spi-rx-bus-width = <8>;

	};

};



&lpuart5 {

	/* console */

	pinctrl-names = "default", "sleep";
@@ -159,6 +174,23 @@ MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 
		>;

	};



	pinctrl_flexspi2_ptd: flexspi2ptdgrp {

		fsl,pins = <



			MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B	0x42

			MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK	0x42

			MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3	0x42

			MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2	0x42

			MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1	0x42

			MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0	0x42

			MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS	0x42

			MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7	0x42

			MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6	0x42

			MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5	0x42

			MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4	0x42

		>;

	};



	pinctrl_lpuart5: lpuart5grp {

		fsl,pins = <

			MX8ULP_PAD_PTF14__LPUART5_TX	0x3