Commit 3dd20b71 authored by Nancy.Lin's avatar Nancy.Lin Committed by Matthias Brugger
Browse files

soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 



Add four mmsys config APIs. The config APIs are used for config
mmsys reg. Some mmsys regs need to be set according to the
HW engine binding to the mmsys simultaneously.

1. mtk_mmsys_merge_async_config: config merge async width/height.
   async is used for cross-clock domain synchronization.
2. mtk_mmsys_hdr_confing: config hdr backend async width/height.
3. mtk_mmsys_mixer_in_config and mtk_mmsys_mixer_in_config:
   config mixer related settings.

Signed-off-by: default avatarNancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarCK Hu <ck.hu@mediatek.com>
Tested-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: default avatarBo-Chen Chen <rex-bc.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230113104434.28023-7-nancy.lin@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 0a815034

drivers/soc/mediatek/mt8195-mmsys.h

+6 −0
Original line number Diff line number Diff line
@@ -75,6 +75,12 @@ 
#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)

#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)



#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD				0xe30

#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD				0xe70

#define MT8195_VDO1_HDR_TOP_CFG					0xd00

#define MT8195_VDO1_MIXER_IN1_ALPHA				0xd30

#define MT8195_VDO1_MIXER_IN1_PAD				0xd40



#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN			0xf04

#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0			1

drivers/soc/mediatek/mtk-mmsys.c

+35 −0
Original line number Diff line number Diff line
@@ -145,6 +145,41 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, 
}

EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);



void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height)

{

	mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx,

			      ~0, height << 16 | width);

}

EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config);



void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height)

{

	mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0,

			      be_height << 16 | be_width);

}

EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config);



void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,

			       u8 mode, u32 biwidth)

{

	struct mtk_mmsys *mmsys = dev_get_drvdata(dev);



	mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0,

			      alpha << 16 | alpha);

	mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx),

			      alpha_sel << (19 + idx));

	mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,

			      GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode);

}

EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);



void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap)

{

	mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,

			      BIT(4), channel_swap << 4);

}

EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap);



void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)

{

	struct mtk_mmsys *mmsys = dev_get_drvdata(dev);

include/linux/soc/mediatek/mtk-mmsys.h

+9 −0
Original line number Diff line number Diff line
@@ -83,4 +83,13 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, 


void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);



void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height);



void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height);



void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,

			       u8 mode, u32 biwidth);



void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap);



#endif /* __MTK_MMSYS_H */