Unverified Commit 3deeb5b0 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'mvebu-dt64-6.2-1' of... 

Merge tag 'mvebu-dt64-6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt

mvebu dt64 for 6.2 (part 1)

Update cache properties for various Marvell SoCs
Reserved memory for optee firmware
Turris Mox (Armada 3720 based Socs)
 - Define slot-power-limit-milliwatt for PCIe
 - Add missing interrupt for RTC

* tag 'mvebu-dt64-6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
  arm64: dts: marvell: add optee FW definitions
  arm64: dts: Update cache properties for marvell
  arm64: dts: armada-3720-turris-mox: Add missing interrupt for RTC
  arm64: dts: armada-3720-turris-mox: Define slot-power-limit-milliwatt for PCIe

Link: https://lore.kernel.org/r/87fse39aer.fsf@BL-laptop


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents ca1a1892 99d2900f

arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ cpu1: cpu@1 { 


		l2: l2-cache {

			compatible = "cache";

			cache-level = <2>;

		};

	};

arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts

+4 −0
Original line number Diff line number Diff line
@@ -125,9 +125,12 @@ &i2c0 { 
	/delete-property/ mrvl,i2c-fast-mode;

	status = "okay";



	/* MCP7940MT-I/MNY RTC */

	rtc@6f {

		compatible = "microchip,mcp7940x";

		reg = <0x6f>;

		interrupt-parent = <&gpiosb>;

		interrupts = <5 0>; /* GPIO2_5 */

	};

};
@@ -136,6 +139,7 @@ &pcie0 { 
	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;

	status = "okay";

	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;

	slot-power-limit-milliwatt = <10000>;

	/*

	 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property

	 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and

arch/arm64/boot/dts/marvell/armada-37xx.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -35,6 +35,11 @@ psci-area@4000000 { 
			reg = <0 0x4000000 0 0x200000>;

			no-map;

		};



		tee@4400000 {

			reg = <0 0x4400000 0 0x1000000>;

			no-map;

		};

	};



	cpus {

arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ l2: l2-cache { 
			cache-size = <0x80000>;

			cache-line-size = <64>;

			cache-sets = <512>;

			cache-level = <2>;

		};

	};

arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ l2_0: l2-cache0 { 
			cache-size = <0x80000>;

			cache-line-size = <64>;

			cache-sets = <512>;

			cache-level = <2>;

		};



		l2_1: l2-cache1 {
@@ -88,6 +89,7 @@ l2_1: l2-cache1 { 
			cache-size = <0x80000>;

			cache-line-size = <64>;

			cache-sets = <512>;

			cache-level = <2>;

		};

	};

};