Commit 3e454860 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
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drm/amd/powerplay: support xgmi pstate setting on powerplay routine V2



Add xgmi pstate setting on powerplay routine.

V2: split the change of is_support_sw_smu_xgmi into a separate patch

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 086e1c56
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+5 −0
Original line number Diff line number Diff line
@@ -285,6 +285,11 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)

	if (is_support_sw_smu_xgmi(adev))
		ret = smu_set_xgmi_pstate(&adev->smu, pstate);
	else if (adev->powerplay.pp_funcs &&
		 adev->powerplay.pp_funcs->set_xgmi_pstate)
		ret = adev->powerplay.pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
								pstate);

	if (ret)
		dev_err(adev->dev,
			"XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
+4 −0
Original line number Diff line number Diff line
@@ -220,6 +220,9 @@ enum pp_df_cstate {
		((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
		(support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)

#define XGMI_MODE_PSTATE_D3 0
#define XGMI_MODE_PSTATE_D0 1

struct seq_file;
enum amd_pp_clock_type;
struct amd_pp_simple_clock_info;
@@ -318,6 +321,7 @@ struct amd_pm_funcs {
	int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
	int (*asic_reset_mode_2)(void *handle);
	int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
	int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
};

#endif
+18 −0
Original line number Diff line number Diff line
@@ -1566,6 +1566,23 @@ static int pp_set_df_cstate(void *handle, enum pp_df_cstate state)
	return 0;
}

static int pp_set_xgmi_pstate(void *handle, uint32_t pstate)
{
	struct pp_hwmgr *hwmgr = handle;

	if (!hwmgr)
		return -EINVAL;

	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate)
		return 0;

	mutex_lock(&hwmgr->smu_lock);
	hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate);
	mutex_unlock(&hwmgr->smu_lock);

	return 0;
}

static const struct amd_pm_funcs pp_dpm_funcs = {
	.load_firmware = pp_dpm_load_fw,
	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
@@ -1625,4 +1642,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
	.asic_reset_mode_2 = pp_asic_reset_mode_2,
	.smu_i2c_bus_access = pp_smu_i2c_bus_access,
	.set_df_cstate = pp_set_df_cstate,
	.set_xgmi_pstate = pp_set_xgmi_pstate,
};
+15 −0
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@@ -4176,6 +4176,20 @@ static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr,
	return ret;
}

static int vega20_set_xgmi_pstate(struct pp_hwmgr *hwmgr,
				  uint32_t pstate)
{
	int ret;

	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
						  PPSMC_MSG_SetXgmiMode,
						  pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
	if (ret)
		pr_err("SetXgmiPstate failed!\n");

	return ret;
}

static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
	/* init/fini related */
	.backend_init = vega20_hwmgr_backend_init,
@@ -4245,6 +4259,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
	.set_mp1_state = vega20_set_mp1_state,
	.smu_i2c_bus_access = vega20_smu_i2c_bus_access,
	.set_df_cstate = vega20_set_df_cstate,
	.set_xgmi_pstate = vega20_set_xgmi_pstate,
};

int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
+1 −0
Original line number Diff line number Diff line
@@ -356,6 +356,7 @@ struct pp_hwmgr_func {
	int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
	int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
	int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
	int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
};

struct pp_table_func {
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