Commit 3ed1db90 authored by Yoshihiro Kaneko's avatar Yoshihiro Kaneko Committed by Geert Uytterhoeven
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arm64: dts: renesas: r8a77995: Add cpg reset for DU 



Add CPG reset properties to DU node of D3 (r8a77995) SoC.

According to Laurent Pinchart, R-Car Gen3 reset is handled at the group
level so specifying one reset entry per group is sufficient.

This patch was inspired by a patch in the BSP by
Takeshi Kihara <takeshi.kihara.df@renesas.com>.

Signed-off-by: default avatarYoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 4193a392

arch/arm64/boot/dts/renesas/r8a77995.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -1001,6 +1001,8 @@ du: display@feb00000 { 
			clocks = <&cpg CPG_MOD 724>,

				 <&cpg CPG_MOD 723>;

			clock-names = "du.0", "du.1";

			resets = <&cpg 724>;

			reset-names = "du.0";

			vsps = <&vspd0 0 &vspd1 0>;

			status = "disabled";