Commit 4147864e authored by Alon Mizrahi's avatar Alon Mizrahi Committed by Oded Gabbay
Browse files

habanalabs: fetch pll frequency from firmware 



Once firmware security is enabled, driver must fetch pll frequencies
through the firmware message interface instead of reading the registers
directly.

Signed-off-by: default avatarAlon Mizrahi <amizrahi@habana.ai>
Reviewed-by: default avatarOded Gabbay <ogabbay@kernel.org>
Signed-off-by: default avatarOded Gabbay <ogabbay@kernel.org>
parent 5c05487f

drivers/misc/habanalabs/common/firmware_if.c

+15 −9
Original line number Diff line number Diff line
@@ -279,7 +279,8 @@ int hl_fw_send_heartbeat(struct hl_device *hdev) 
	return rc;

}



int hl_fw_cpucp_info_get(struct hl_device *hdev)

int hl_fw_cpucp_info_get(struct hl_device *hdev,

			u32 cpu_security_boot_status_reg)

{

	struct asic_fixed_properties *prop = &hdev->asic_prop;

	struct cpucp_packet pkt = {};
@@ -324,6 +325,11 @@ int hl_fw_cpucp_info_get(struct hl_device *hdev) 
		goto out;

	}



	/* Read FW application security bits again */

	if (hdev->asic_prop.fw_security_status_valid)

		hdev->asic_prop.fw_app_security_map =

				RREG32(cpu_security_boot_status_reg);



out:

	hdev->asic_funcs->cpu_accessible_dma_pool_free(hdev,

			sizeof(struct cpucp_info), cpucp_info_cpu_addr);
@@ -446,10 +452,8 @@ int hl_fw_cpucp_total_energy_get(struct hl_device *hdev, u64 *total_energy) 
	return rc;

}



int hl_fw_cpucp_pll_info_get(struct hl_device *hdev,

		enum cpucp_pll_type_attributes pll_type,

		enum cpucp_pll_reg_attributes pll_reg,

		u32 *pll_info)

int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, u16 pll_index,

		u16 *pll_freq_arr)

{

	struct cpucp_packet pkt;

	u64 result;
@@ -457,17 +461,19 @@ int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, 


	memset(&pkt, 0, sizeof(pkt));



	pkt.ctl = cpu_to_le32(CPUCP_PACKET_PLL_REG_GET <<

	pkt.ctl = cpu_to_le32(CPUCP_PACKET_PLL_INFO_GET <<

				CPUCP_PKT_CTL_OPCODE_SHIFT);

	pkt.pll_type = __cpu_to_le16(pll_type);

	pkt.pll_reg = __cpu_to_le16(pll_reg);

	pkt.pll_type = __cpu_to_le16(pll_index);



	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),

			HL_CPUCP_INFO_TIMEOUT_USEC, &result);

	if (rc)

		dev_err(hdev->dev, "Failed to read PLL info, error %d\n", rc);



	*pll_info = (u32) result;

	pll_freq_arr[0] = FIELD_GET(CPUCP_PKT_RES_PLL_OUT0_MASK, result);

	pll_freq_arr[1] = FIELD_GET(CPUCP_PKT_RES_PLL_OUT1_MASK, result);

	pll_freq_arr[2] = FIELD_GET(CPUCP_PKT_RES_PLL_OUT2_MASK, result);

	pll_freq_arr[3] = FIELD_GET(CPUCP_PKT_RES_PLL_OUT3_MASK, result);



	return rc;

}

drivers/misc/habanalabs/common/habanalabs.h

+4 −5
Original line number Diff line number Diff line
@@ -2191,16 +2191,15 @@ void *hl_fw_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size, 
void hl_fw_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,

					void *vaddr);

int hl_fw_send_heartbeat(struct hl_device *hdev);

int hl_fw_cpucp_info_get(struct hl_device *hdev);

int hl_fw_cpucp_info_get(struct hl_device *hdev,

			u32 cpu_security_boot_status_reg);

int hl_fw_get_eeprom_data(struct hl_device *hdev, void *data, size_t max_size);

int hl_fw_cpucp_pci_counters_get(struct hl_device *hdev,

		struct hl_info_pci_counters *counters);

int hl_fw_cpucp_total_energy_get(struct hl_device *hdev,

			u64 *total_energy);

int hl_fw_cpucp_pll_info_get(struct hl_device *hdev,

		enum cpucp_pll_type_attributes pll_type,

		enum cpucp_pll_reg_attributes pll_reg,

		u32 *pll_info);

int hl_fw_cpucp_pll_info_get(struct hl_device *hdev, u16 pll_index,

		u16 *pll_freq_arr);

int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg,

			u32 msg_to_cpu_reg, u32 cpu_msg_status_reg,

			u32 cpu_security_boot_status_reg, u32 boot_err0_reg,

drivers/misc/habanalabs/common/habanalabs_ioctl.c

+22 −0
Original line number Diff line number Diff line
@@ -403,6 +403,25 @@ static int total_energy_consumption_info(struct hl_fpriv *hpriv, 
		min((size_t) max_size, sizeof(total_energy))) ? -EFAULT : 0;

}



static int pll_frequency_info(struct hl_fpriv *hpriv, struct hl_info_args *args)

{

	struct hl_device *hdev = hpriv->hdev;

	struct hl_pll_frequency_info freq_info = {0};

	u32 max_size = args->return_size;

	void __user *out = (void __user *) (uintptr_t) args->return_pointer;

	int rc;



	if ((!max_size) || (!out))

		return -EINVAL;



	rc = hl_fw_cpucp_pll_info_get(hdev, args->pll_index, freq_info.output);

	if (rc)

		return rc;



	return copy_to_user(out, &freq_info,

		min((size_t) max_size, sizeof(freq_info))) ? -EFAULT : 0;

}



static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data,

				struct device *dev)

{
@@ -480,6 +499,9 @@ static int _hl_info_ioctl(struct hl_fpriv *hpriv, void *data, 
	case HL_INFO_TOTAL_ENERGY:

		return total_energy_consumption_info(hpriv, args);



	case HL_INFO_PLL_FREQUENCY:

		return pll_frequency_info(hpriv, args);



	default:

		dev_err(dev, "Invalid request %d\n", args->op);

		rc = -ENOTTY;

drivers/misc/habanalabs/gaudi/gaudi.c

+91 −44
Original line number Diff line number Diff line
@@ -103,6 +103,8 @@ 


#define HBM_SCRUBBING_TIMEOUT_US	1000000 /* 1s */



#define GAUDI_PLL_MAX 10



static const char gaudi_irq_name[GAUDI_MSI_ENTRIES][GAUDI_MAX_STRING_LEN] = {

		"gaudi cq 0_0", "gaudi cq 0_1", "gaudi cq 0_2", "gaudi cq 0_3",

		"gaudi cq 1_0", "gaudi cq 1_1", "gaudi cq 1_2", "gaudi cq 1_3",
@@ -149,6 +151,19 @@ static const u16 gaudi_packet_sizes[MAX_PACKET_ID] = { 
	[PACKET_LOAD_AND_EXE]	= sizeof(struct packet_load_and_exe)

};



static const u32 gaudi_pll_base_addresses[GAUDI_PLL_MAX] = {

	[CPU_PLL] = mmPSOC_CPU_PLL_NR,

	[PCI_PLL] = mmPSOC_PCI_PLL_NR,

	[SRAM_PLL] = mmSRAM_W_PLL_NR,

	[HBM_PLL] = mmPSOC_HBM_PLL_NR,

	[NIC_PLL] = mmNIC0_PLL_NR,

	[DMA_PLL] = mmDMA_W_PLL_NR,

	[MESH_PLL] = mmMESH_W_PLL_NR,

	[MME_PLL] = mmPSOC_MME_PLL_NR,

	[TPC_PLL] = mmPSOC_TPC_PLL_NR,

	[IF_PLL] = mmIF_W_PLL_NR

};



static inline bool validate_packet_id(enum packet_id id)

{

	switch (id) {
@@ -688,61 +703,93 @@ static int gaudi_early_fini(struct hl_device *hdev) 
}



/**

 * gaudi_fetch_psoc_frequency - Fetch PSOC frequency values

 * gaudi_fetch_pll_frequency - Fetch PLL frequency values

 *

 * @hdev: pointer to hl_device structure

 * @pll_index: index of the pll to fetch frequency from

 * @pll_freq: pointer to store the pll frequency in MHz in each of the available

 *            outputs. if a certain output is not available a 0 will be set

 *

 */

static int gaudi_fetch_psoc_frequency(struct hl_device *hdev)

static int gaudi_fetch_pll_frequency(struct hl_device *hdev,

				enum gaudi_pll_index pll_index,

				u16 *pll_freq_arr)

{

	struct asic_fixed_properties *prop = &hdev->asic_prop;

	u32 trace_freq = 0, pll_clk = 0;

	u32 div_fctr, div_sel, nr, nf, od;

	int rc;

	u32 nr = 0, nf = 0, od = 0, pll_clk = 0, div_fctr, div_sel,

			pll_base_addr = gaudi_pll_base_addresses[pll_index];

	u16 freq = 0;

	int i, rc;



	if (hdev->asic_prop.fw_security_status_valid &&

			(hdev->asic_prop.fw_app_security_map &

					CPU_BOOT_DEV_STS0_PLL_INFO_EN)) {

		rc = hl_fw_cpucp_pll_info_get(hdev, pll_index, pll_freq_arr);



	if (hdev->asic_prop.fw_security_disabled) {

		div_fctr = RREG32(mmPSOC_CPU_PLL_DIV_FACTOR_2);

		div_sel = RREG32(mmPSOC_CPU_PLL_DIV_SEL_2);

		nr = RREG32(mmPSOC_CPU_PLL_NR);

		nf = RREG32(mmPSOC_CPU_PLL_NF);

		od = RREG32(mmPSOC_CPU_PLL_OD);

	} else {

		rc = hl_fw_cpucp_pll_info_get(hdev, cpucp_pll_cpu,

				cpucp_pll_div_factor_reg, &div_fctr);

		rc |= hl_fw_cpucp_pll_info_get(hdev, cpucp_pll_cpu,

				cpucp_pll_div_sel_reg, &div_sel);

		rc |= hl_fw_cpucp_pll_info_get(hdev, cpucp_pll_cpu,

				cpucp_pll_nr_reg, &nr);

		rc |= hl_fw_cpucp_pll_info_get(hdev, cpucp_pll_cpu,

				cpucp_pll_nf_reg, &nf);

		rc |= hl_fw_cpucp_pll_info_get(hdev, cpucp_pll_cpu,

				cpucp_pll_od_reg, &od);

		if (rc)

			return rc;

	}



	if (div_sel == DIV_SEL_REF_CLK || div_sel == DIV_SEL_DIVIDED_REF) {

	} else if (hdev->asic_prop.fw_security_disabled) {

		/* Backward compatibility */

		nr = RREG32(pll_base_addr + PLL_NR_OFFSET);

		nf = RREG32(pll_base_addr + PLL_NF_OFFSET);

		od = RREG32(pll_base_addr + PLL_OD_OFFSET);



		for (i = 0; i < HL_PLL_NUM_OUTPUTS; i++) {

			div_fctr = RREG32(pll_base_addr +

					PLL_DIV_FACTOR_0_OFFSET + i * 4);

			div_sel = RREG32(pll_base_addr +

					PLL_DIV_SEL_0_OFFSET + i * 4);



			if (div_sel == DIV_SEL_REF_CLK ||

				div_sel == DIV_SEL_DIVIDED_REF) {

				if (div_sel == DIV_SEL_REF_CLK)

			trace_freq = PLL_REF_CLK;

					freq = PLL_REF_CLK;

				else

			trace_freq = PLL_REF_CLK / (div_fctr + 1);

					freq = PLL_REF_CLK / (div_fctr + 1);

			} else if (div_sel == DIV_SEL_PLL_CLK ||

					div_sel == DIV_SEL_DIVIDED_PLL) {

		pll_clk = PLL_REF_CLK * (nf + 1) / ((nr + 1) * (od + 1));

				pll_clk = PLL_REF_CLK * (nf + 1) /

						((nr + 1) * (od + 1));

				if (div_sel == DIV_SEL_PLL_CLK)

			trace_freq = pll_clk;

					freq = pll_clk;

				else

			trace_freq = pll_clk / (div_fctr + 1);

					freq = pll_clk / (div_fctr + 1);

			} else {

				dev_warn(hdev->dev,

			"Received invalid div select value: %d", div_sel);

					"Received invalid div select value: %d",

					div_sel);

			}



	prop->psoc_timestamp_frequency = trace_freq;

	prop->psoc_pci_pll_nr = nr;

	prop->psoc_pci_pll_nf = nf;

	prop->psoc_pci_pll_od = od;

	prop->psoc_pci_pll_div_factor = div_fctr;

			pll_freq_arr[i] = freq;

		}

	} else {

		dev_err(hdev->dev, "Failed to fetch PLL frequency values\n");

		return -EIO;

	}



	return 0;

}



/**

 * gaudi_fetch_psoc_frequency - Fetch PSOC frequency values

 *

 * @hdev: pointer to hl_device structure

 *

 */

static int gaudi_fetch_psoc_frequency(struct hl_device *hdev)

{

	struct asic_fixed_properties *prop = &hdev->asic_prop;

	u16 pll_freq[HL_PLL_NUM_OUTPUTS];

	int rc;



	rc = gaudi_fetch_pll_frequency(hdev, CPU_PLL, pll_freq);

	if (rc)

		return rc;



	prop->psoc_timestamp_frequency = pll_freq[2];

	prop->psoc_pci_pll_nr = 0;

	prop->psoc_pci_pll_nf = 0;

	prop->psoc_pci_pll_od = 0;

	prop->psoc_pci_pll_div_factor = 0;



	return 0;

}
@@ -7438,7 +7485,7 @@ static int gaudi_cpucp_info_get(struct hl_device *hdev) 
	if (!(gaudi->hw_cap_initialized & HW_CAP_CPU_Q))

		return 0;



	rc = hl_fw_cpucp_info_get(hdev);

	rc = hl_fw_cpucp_info_get(hdev, mmCPU_BOOT_DEV_STS0);

	if (rc)

		return rc;

drivers/misc/habanalabs/gaudi/gaudiP.h

+8 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include "../include/gaudi/gaudi_packets.h"

#include "../include/gaudi/gaudi.h"

#include "../include/gaudi/gaudi_async_events.h"

#include "../include/gaudi/gaudi_fw_if.h"



#define NUMBER_OF_EXT_HW_QUEUES		8

#define NUMBER_OF_CMPLT_QUEUES		NUMBER_OF_EXT_HW_QUEUES
@@ -104,6 +105,13 @@ 
#define MME_ACC_OFFSET		(mmMME1_ACC_BASE - mmMME0_ACC_BASE)

#define SRAM_BANK_OFFSET	(mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE)



#define PLL_NR_OFFSET		0

#define PLL_NF_OFFSET		(mmPSOC_CPU_PLL_NF - mmPSOC_CPU_PLL_NR)

#define PLL_OD_OFFSET		(mmPSOC_CPU_PLL_OD - mmPSOC_CPU_PLL_NR)

#define PLL_DIV_FACTOR_0_OFFSET	(mmPSOC_CPU_PLL_DIV_FACTOR_0 - \

				mmPSOC_CPU_PLL_NR)

#define PLL_DIV_SEL_0_OFFSET	(mmPSOC_CPU_PLL_DIV_SEL_0 - mmPSOC_CPU_PLL_NR)



#define NUM_OF_SOB_IN_BLOCK		\

	(((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \

	mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)