Unverified Commit 418d2b2f authored by Yong Zhi's avatar Yong Zhi Committed by Mark Brown
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ASoC: SOF: Intel: mtl: Access MTL_HFPWRCTL from HDA_DSP_BAR 



The Host Power Management/Clock Control (ULP) Registers in
the HDA BAR shadow the values of the same registers in the DSP BAR,
so let's modify the latter - as done already for other accesses.

Signed-off-by: default avatarYong Zhi <yong.zhi@intel.com>
Reviewed-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20230307095251.3058-1-peter.ujfalusi@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1d045d77

sound/soc/sof/intel/mtl.c

+1 −1
Original line number Diff line number Diff line
@@ -256,7 +256,7 @@ static int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev) 
		dev_err(sdev->dev, "failed to power up gated DSP domain\n");



	/* make sure SoundWire is not power-gated */

	snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, MTL_HFPWRCTL,

	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,

				MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1));

	return ret;

}