Unverified Commit 41cb85bc authored by V sujith kumar Reddy's avatar V sujith kumar Reddy Committed by Mark Brown
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ASoC: SOF: amd: Add support for Rembrandt plaform. 



Add pci driver and platform driver to enable SOF support on ACP6x
architecture based Rembrandt platform.

Signed-off-by: default avatarAjit Kumar Pandey <AjitKumar.Pandey@amd.com>
Signed-off-by: default avatarV sujith kumar Reddy <Vsujithkumar.Reddy@amd.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220913144319.1055302-3-Vsujithkumar.Reddy@amd.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 4da6b033

sound/soc/sof/amd/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -31,4 +31,14 @@ config SND_SOC_SOF_AMD_RENOIR 
	select SND_SOC_SOF_AMD_COMMON

	help

	  Select this option for SOF support on AMD Renoir platform



config SND_SOC_SOF_AMD_REMBRANDT

	tristate "SOF support for REMBRANDT"

	depends on SND_SOC_SOF_PCI

	select SND_SOC_SOF_AMD_COMMON

	help

	  Select this option for SOF support on AMD Rembrandt platform

	  Say Y if you want to enable SOF on Rembrandt.

	  If unsure select "N".



endif

sound/soc/sof/amd/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -6,6 +6,8 @@ 


snd-sof-amd-acp-objs := acp.o acp-loader.o acp-ipc.o acp-pcm.o acp-stream.o acp-trace.o acp-common.o

snd-sof-amd-renoir-objs := pci-rn.o renoir.o

snd-sof-amd-rembrandt-objs := pci-rmb.o rembrandt.o



obj-$(CONFIG_SND_SOC_SOF_AMD_COMMON) += snd-sof-amd-acp.o

obj-$(CONFIG_SND_SOC_SOF_AMD_RENOIR) +=snd-sof-amd-renoir.o

obj-$(CONFIG_SND_SOC_SOF_AMD_REMBRANDT) +=snd-sof-amd-rembrandt.o

sound/soc/sof/amd/acp-dsp-offset.h

+7 −1
Original line number Diff line number Diff line
@@ -49,22 +49,28 @@ 
#define ACP_CONTROL				0x1004



#define ACP3X_I2S_PIN_CONFIG			0x1400

#define ACP6X_I2S_PIN_CONFIG			0x1440



/* Registers offsets from ACP_PGFSM block */

#define ACP3X_PGFSM_BASE			0x141C

#define ACP6X_PGFSM_BASE                        0x1024

#define PGFSM_CONTROL_OFFSET			0x0

#define PGFSM_STATUS_OFFSET			0x4

#define ACP3X_CLKMUX_SEL			0x1424

#define ACP6X_CLKMUX_SEL			0x102C



/* Registers from ACP_INTR block */

#define ACP3X_EXT_INTR_STAT			0x1808

#define ACP6X_EXT_INTR_STAT                     0x1A0C



#define ACP3X_DSP_SW_INTR_BASE			0x1814

#define ACP6X_DSP_SW_INTR_BASE                  0x1808

#define DSP_SW_INTR_CNTL_OFFSET			0x0

#define DSP_SW_INTR_STAT_OFFSET			0x4

#define DSP_SW_INTR_TRIG_OFFSET			0x8

#define ACP_ERROR_STATUS			0x18C4

#define ACP3X_AXI2DAGB_SEM_0			0x1880

#define ACP6X_AXI2DAGB_SEM_0			0x1874



/* Registers from ACP_SHA block */

#define ACP_SHA_DSP_FW_QUALIFIER		0x1C70
@@ -78,5 +84,5 @@ 
#define ACP_SHA_PSP_ACK                         0x1C74



#define ACP_SCRATCH_REG_0			0x10000



#define ACP6X_DSP_FUSION_RUNSTALL		0x0644

#endif

sound/soc/sof/amd/acp-loader.c

+7 −0
Original line number Diff line number Diff line
@@ -198,12 +198,19 @@ EXPORT_SYMBOL_NS(acp_dsp_pre_fw_run, SND_SOC_SOF_AMD_COMMON); 


int acp_sof_dsp_run(struct snd_sof_dev *sdev)

{

	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);

	int val;



	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_RUNSTALL, ACP_DSP_RUN);

	val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DSP0_RUNSTALL);

	dev_dbg(sdev->dev, "ACP_DSP0_RUNSTALL : 0x%0x\n", val);



	/* Some platforms won't support fusion DSP,keep offset zero for no support */

	if (desc->fusion_dsp_offset) {

		snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->fusion_dsp_offset, ACP_DSP_RUN);

		val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->fusion_dsp_offset);

		dev_dbg(sdev->dev, "ACP_DSP0_FUSION_RUNSTALL : 0x%0x\n", val);

	}

	return 0;

}

EXPORT_SYMBOL_NS(acp_sof_dsp_run, SND_SOC_SOF_AMD_COMMON);

sound/soc/sof/amd/acp.h

+5 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 


#define ACP_DSP_INTR_EN_MASK			0x00000001

#define ACP3X_SRAM_PTE_OFFSET			0x02050000

#define ACP6X_SRAM_PTE_OFFSET			0x03800000

#define PAGE_SIZE_4K_ENABLE			0x2

#define ACP_PAGE_SIZE				0x1000

#define ACP_DMA_CH_RUN				0x02
@@ -54,6 +55,7 @@ 
#define ACP_DSP_TO_HOST_IRQ			0x04



#define HOST_BRIDGE_CZN				0x1630

#define HOST_BRIDGE_RMB				0x14B5

#define ACP_SHA_STAT				0x8000

#define ACP_PSP_TIMEOUT_COUNTER			5

#define ACP_EXT_INTR_ERROR_STAT			0x20000000
@@ -150,6 +152,7 @@ struct sof_amd_acp_desc { 
	u32 i2s_pin_config_offset;

	u32 hw_semaphore_offset;

	u32 acp_clkmux_sel;

	u32 fusion_dsp_offset;

};



/* Common device data struct for ACP devices */
@@ -223,6 +226,8 @@ extern struct snd_sof_dsp_ops sof_acp_common_ops; 


extern struct snd_sof_dsp_ops sof_renoir_ops;

int sof_renoir_ops_init(struct snd_sof_dev *sdev);

extern struct snd_sof_dsp_ops sof_rembrandt_ops;

int sof_rembrandt_ops_init(struct snd_sof_dev *sdev);



int acp_dai_probe(struct snd_soc_dai *dai);

struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev);