Commit 41f1a01b authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'ptp-ptp_clockmatrix-Fix-output-1-PPS-alignment' 



Vincent Cheng says:

====================
ptp: ptp_clockmatrix: Fix output 1 PPS alignment.

This series fixes a race condition that may result in the output clock
not aligned to internal 1 PPS clock.

Part of device initialization is to align the rising edge of output
clocks to the internal rising edge of the 1 PPS clock.  If the system
APLL and DPLL are not locked when this alignment occurs, the alignment
fails and a fixed offset between the internal 1 PPS clock and the
output clock occurs.

If a clock is dynamically enabled after power-up, the output clock
also needs to be aligned to the internal 1 PPS clock.

v3:
Suggested by: Jakub Kicinski <kuba@kernel.org>
- Remove unnecessary 'err' variable
- Increase msleep()/loop accuracy by using jiffies in while()
- No empty lines between variables
- No empty lines between call and the if
- parenthesis around a == b are unnecessary
- Inconsistent \n usage in dev_()
- Remove unnecessary empty line
- Leave string format in place so static code checkers can
  validate arguments

v2:
Suggested by: Richard Cochran <richardcochran@gmail.com>
- Added const to "char * fmt"
- Break unrelated header change into separate patch
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 85749080 77fdb168

drivers/ptp/idt8a340_reg.h

+10 −0
Original line number Diff line number Diff line
@@ -122,6 +122,8 @@ 
#define OTP_SCSR_CONFIG_SELECT            0x0022



#define STATUS                            0xc03c

#define DPLL_SYS_STATUS                   0x0020

#define DPLL_SYS_APLL_STATUS              0x0021

#define USER_GPIO0_TO_7_STATUS            0x008a

#define USER_GPIO8_TO_15_STATUS           0x008b
@@ -707,4 +709,12 @@ 
/* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */

#define COMBO_MASTER_HOLD                 BIT(0)



/* Bit definitions for DPLL_SYS_STATUS register */

#define DPLL_SYS_STATE_MASK               (0xf)



/* Bit definitions for SYS_APLL_STATUS register */

#define SYS_APLL_LOSS_LOCK_LIVE_MASK       BIT(0)

#define SYS_APLL_LOSS_LOCK_LIVE_LOCKED     0

#define SYS_APLL_LOSS_LOCK_LIVE_UNLOCKED   1



#endif

drivers/ptp/ptp_clockmatrix.c

+137 −176

File changed.

Preview size limit exceeded, changes collapsed.

drivers/ptp/ptp_clockmatrix.h

+15 −2
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ 
#define FW_FILENAME	"idtcm.bin"

#define MAX_TOD		(4)

#define MAX_PLL		(8)

#define MAX_OUTPUT	(12)



#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
@@ -51,6 +50,9 @@ 
#define TOD_WRITE_OVERHEAD_COUNT_MAX		(2)

#define TOD_BYTE_COUNT				(11)



#define LOCK_TIMEOUT_MS			(2000)

#define LOCK_POLL_INTERVAL_MS		(10)



#define PEROUT_ENABLE_OUTPUT_MASK	(0xdeadbeef)



#define IDTCM_MAX_WRITE_COUNT		(512)
@@ -105,6 +107,18 @@ enum scsr_tod_write_type_sel { 
	SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS,

};



/* Values STATUS.DPLL_SYS_STATUS.DPLL_SYS_STATE */

enum dpll_state {

	DPLL_STATE_MIN = 0,

	DPLL_STATE_FREERUN = DPLL_STATE_MIN,

	DPLL_STATE_LOCKACQ = 1,

	DPLL_STATE_LOCKREC = 2,

	DPLL_STATE_LOCKED = 3,

	DPLL_STATE_HOLDOVER = 4,

	DPLL_STATE_OPEN_LOOP = 5,

	DPLL_STATE_MAX = DPLL_STATE_OPEN_LOOP,

};



struct idtcm;



struct idtcm_channel {
@@ -123,7 +137,6 @@ struct idtcm_channel { 
	enum pll_mode		pll_mode;

	u8			pll;

	u16			output_mask;

	u8			output_phase_adj[MAX_OUTPUT][4];

};



struct idtcm {