Commit 420f63cb authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/mst: update slot information for 128b/132b 



128b/132b supports using 64 slots starting from 0, while 8b/10b reserves
slot 0 for metadata.

Commit d6c6a76f ("drm: Update MST First Link Slot Information Based
on Encoding Format") added support for updating the topology state
accordingly, and commit 41724ea2 ("drm/amd/display: Add DP 2.0 MST
DM Support") started using it in the amd driver.

This feels more than a little cumbersome, especially updating the
information in atomic check. For i915, add the update to MST connector
.compute_config hook rather than iterating over all MST managers and
connectors in global mode config .atomic_check. Fingers crossed.

v3:
- Propagate errors from intel_dp_mst_update_slots() (Ville)

v2:
- Update in .compute_config() not .atomic_check (Ville)

Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Cc: Lyude Paul <lyude@redhat.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: default avatarLyude Paul <lyude@redhat.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220208152317.3019070-1-jani.nikula@intel.com
parent 3ee7fab0

drivers/gpu/drm/i915/display/intel_dp_mst.c

+31 −2
Original line number Diff line number Diff line
@@ -99,6 +99,29 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, 
	return 0;

}



static int intel_dp_mst_update_slots(struct intel_encoder *encoder,

				     struct intel_crtc_state *crtc_state,

				     struct drm_connector_state *conn_state)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);

	struct intel_dp *intel_dp = &intel_mst->primary->dp;

	struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;

	struct drm_dp_mst_topology_state *topology_state;

	u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?

		DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;



	topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);

	if (IS_ERR(topology_state)) {

		drm_dbg_kms(&i915->drm, "slot update failed\n");

		return PTR_ERR(topology_state);

	}



	drm_dp_mst_update_slots(topology_state, link_coding_cap);



	return 0;

}



static int intel_dp_mst_compute_config(struct intel_encoder *encoder,

				       struct intel_crtc_state *pipe_config,

				       struct drm_connector_state *conn_state)
@@ -155,6 +178,10 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, 
	if (ret)

		return ret;



	ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);

	if (ret)

		return ret;



	pipe_config->limited_color_range =

		intel_dp_limited_color_range(pipe_config, conn_state);
@@ -357,6 +384,7 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, 
	struct intel_connector *connector =

		to_intel_connector(old_conn_state->connector);

	struct drm_i915_private *i915 = to_i915(connector->base.dev);

	int start_slot = intel_dp_is_uhbr(old_crtc_state) ? 0 : 1;

	int ret;



	drm_dbg_kms(&i915->drm, "active links %d\n",
@@ -366,7 +394,7 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, 


	drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port);



	ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr, 1);

	ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr, start_slot);

	if (ret) {

		drm_dbg_kms(&i915->drm, "failed to update payload %d\n", ret);

	}
@@ -475,6 +503,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, 
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_connector *connector =

		to_intel_connector(conn_state->connector);

	int start_slot = intel_dp_is_uhbr(pipe_config) ? 0 : 1;

	int ret;

	bool first_mst_stream;
@@ -509,7 +538,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, 


	intel_dp->active_mst_links++;



	ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr, 1);

	ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr, start_slot);



	/*

	 * Before Gen 12 this is not done as part of