Commit 425fede6 authored by Yifan Zha's avatar Yifan Zha Committed by Alex Deucher
Browse files

drm/amdgpu: Use PSP program IH_RB_CNTL registers under SRIOV 



[Why]
With L1 Policy applied, IH_RB_CNTL/RING cannot be accessed by VF.

[How]
Use PSP program IH_RB_CNTL in VF.

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarYifan Zha <Yifan.Zha@amd.com>
Signed-off-by: default avatarHorace Chen <horace.chen@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f8bd7321

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

+23 −3
Original line number Diff line number Diff line
@@ -105,7 +105,13 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev, 
	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,

				   RB_USED_INT_THRESHOLD, threshold);



	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {

		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))

			return;

	} else {

		WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl);

	}



	WREG32_SOC15(OSSSYS, 0, regIH_CNTL2, ih_cntl);

}
@@ -132,7 +138,13 @@ static int ih_v6_0_toggle_ring_interrupts(struct amdgpu_device *adev, 
	/* enable_intr field is only valid in ring0 */

	if (ih == &adev->irq.ih)

		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));



	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {

		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))

			return -ETIMEDOUT;

	} else {

		WREG32(ih_regs->ih_rb_cntl, tmp);

	}



	if (enable) {

		ih->enabled = true;
@@ -242,7 +254,15 @@ static int ih_v6_0_enable_ring(struct amdgpu_device *adev, 
		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);

		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

	}



	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {

		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {

			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");

			return -ETIMEDOUT;

		}

	} else {

		WREG32(ih_regs->ih_rb_cntl, tmp);

	}



	if (ih == &adev->irq.ih) {

		/* set the ih ring 0 writeback address whether it's enabled or not */