Commit 428384b5 authored Apr 26, 2020 by Stephan Gerhold Committed by Bjorn Andersson May 12, 2020

arm64: dts: qcom: msm8916: Add blsp_i2c1



MSM8916 has another I2C QUP controller that can be enabled on
GPIO 2 and 3.

Add blsp_i2c1 to msm8916.dtsi and disable it by default.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200426140642.204395-2-stephan@gerhold.net


Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

parent 0f1decaa

arch/arm64/boot/dts/qcom/msm8916-pins.dtsi

+24 −0

Original line number	Diff line number	Diff line
		@@ -262,6 +262,30 @@ pinconf {
		};
		};

		i2c1_default: i2c1_default {
		pinmux {
		function = "blsp_i2c1";
		pins = "gpio2", "gpio3";
		};
		pinconf {
		pins = "gpio2", "gpio3";
		drive-strength = <2>;
		bias-disable;
		};
		};

		i2c1_sleep: i2c1_sleep {
		pinmux {
		function = "gpio";
		pins = "gpio2", "gpio3";
		};
		pinconf {
		pins = "gpio2", "gpio3";
		drive-strength = <2>;
		bias-disable;
		};
		};

		i2c2_default: i2c2_default {
		pinmux {
		function = "blsp_i2c2";

arch/arm64/boot/dts/qcom/msm8916.dtsi

+15 −0

Original line number	Diff line number	Diff line
		@@ -612,6 +612,21 @@ blsp_spi6: spi@78ba000 {
		status = "disabled";
		};

		blsp_i2c1: i2c@78b5000 {
		compatible = "qcom,i2c-qup-v2.2.1";
		reg = <0x078b5000 0x500>;
		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&gcc GCC_BLSP1_AHB_CLK>,
		<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
		clock-names = "iface", "core";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&i2c1_default>;
		pinctrl-1 = <&i2c1_sleep>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		};

		blsp_i2c2: i2c@78b6000 {
		compatible = "qcom,i2c-qup-v2.2.1";
		reg = <0x078b6000 0x500>;