Commit 43ca31e0 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/reset' 

- Wait longer for devices to become ready after resume (as we do for reset)
  to accommodate Intel Titan Ridge xHCI devices (Mika Westerberg)

- Drop pci_bridge_wait_for_secondary_bus() timeout parameter since all
  callers pass the same value (Mika Westerberg)

- Extend D3hot delay for NVIDIA HDA controllers to avoid unrecoverable
  devices after a bus reset (Alex Williamson)

* pci/reset:
  PCI/PM: Extend D3hot delay for NVIDIA HDA controllers
  PCI/PM: Drop pci_bridge_wait_for_secondary_bus() timeout parameter
  PCI/PM: Increase wait time after resume
parents cc8a983d a5a6dd26

drivers/pci/pci-driver.c

+2 −1
Original line number Diff line number Diff line
@@ -572,7 +572,8 @@ static void pci_pm_default_resume_early(struct pci_dev *pci_dev) 


static void pci_pm_bridge_power_up_actions(struct pci_dev *pci_dev)

{

	pci_bridge_wait_for_secondary_bus(pci_dev, "resume", PCI_RESET_WAIT);

	pci_bridge_wait_for_secondary_bus(pci_dev, "resume");



	/*

	 * When powering on a bridge from D3cold, the whole hierarchy may be

	 * powered on into D0uninitialized state, resume them to give them a

drivers/pci/pci.c

+12 −6
Original line number Diff line number Diff line
@@ -64,6 +64,14 @@ struct pci_pme_device { 


#define PME_TIMEOUT 1000 /* How long between PME checks */



/*

 * Devices may extend the 1 sec period through Request Retry Status

 * completions (PCIe r6.0 sec 2.3.1).  The spec does not provide an upper

 * limit, but 60 sec ought to be enough for any device to become

 * responsive.

 */

#define PCIE_RESET_READY_POLL_MS 60000 /* msec */



static void pci_dev_d3_sleep(struct pci_dev *dev)

{

	unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
@@ -4939,7 +4947,6 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) 
 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible

 * @dev: PCI bridge

 * @reset_type: reset type in human-readable form

 * @timeout: maximum time to wait for devices on secondary bus (milliseconds)

 *

 * Handle necessary delays before access to the devices on the secondary

 * side of the bridge are permitted after D3cold to D0 transition
@@ -4952,8 +4959,7 @@ static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) 
 * Return 0 on success or -ENOTTY if the first device on the secondary bus

 * failed to become accessible.

 */

int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,

				      int timeout)

int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type)

{

	struct pci_dev *child;

	int delay;
@@ -5031,7 +5037,8 @@ int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type, 
		}

	}



	return pci_dev_wait(child, reset_type, timeout - delay);

	return pci_dev_wait(child, reset_type,

			    PCIE_RESET_READY_POLL_MS - delay);

}



void pci_reset_secondary_bus(struct pci_dev *dev)
@@ -5068,8 +5075,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev) 
{

	pcibios_reset_secondary_bus(dev);



	return pci_bridge_wait_for_secondary_bus(dev, "bus reset",

						 PCIE_RESET_READY_POLL_MS);

	return pci_bridge_wait_for_secondary_bus(dev, "bus reset");

}

EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);

drivers/pci/pci.h

+1 −8
Original line number Diff line number Diff line
@@ -70,12 +70,6 @@ struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 
 * Reset (PCIe r6.0 sec 5.8).

 */

#define PCI_RESET_WAIT		1000	/* msec */

/*

 * Devices may extend the 1 sec period through Request Retry Status completions

 * (PCIe r6.0 sec 2.3.1).  The spec does not provide an upper limit, but 60 sec

 * ought to be enough for any device to become responsive.

 */

#define PCIE_RESET_READY_POLL_MS 60000	/* msec */



void pci_update_current_state(struct pci_dev *dev, pci_power_t state);

void pci_refresh_power_state(struct pci_dev *dev);
@@ -100,8 +94,7 @@ void pci_msix_init(struct pci_dev *dev); 
bool pci_bridge_d3_possible(struct pci_dev *dev);

void pci_bridge_d3_update(struct pci_dev *dev);

void pci_bridge_reconfigure_ltr(struct pci_dev *dev);

int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,

				      int timeout);

int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);



static inline void pci_wakeup_event(struct pci_dev *dev)

{

drivers/pci/pcie/dpc.c

+1 −2
Original line number Diff line number Diff line
@@ -170,8 +170,7 @@ pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) 
	pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,

			      PCI_EXP_DPC_STATUS_TRIGGER);



	if (pci_bridge_wait_for_secondary_bus(pdev, "DPC",

					      PCIE_RESET_READY_POLL_MS)) {

	if (pci_bridge_wait_for_secondary_bus(pdev, "DPC")) {

		clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);

		ret = PCI_ERS_RESULT_DISCONNECT;

	} else {

drivers/pci/quirks.c

+13 −0
Original line number Diff line number Diff line
@@ -1939,6 +1939,19 @@ static void quirk_radeon_pm(struct pci_dev *dev) 
}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);



/*

 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus

 * reset is performed too soon after transition to D0, extend d3hot_delay

 * to previous effective default for all NVIDIA HDA controllers.

 */

static void quirk_nvidia_hda_pm(struct pci_dev *dev)

{

	quirk_d3hot_delay(dev, 20);

}

DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,

			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8,

			      quirk_nvidia_hda_pm);



/*

 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.

 * https://bugzilla.kernel.org/show_bug.cgi?id=205587