Commit 46ad3dc4 authored by Pali Rohár's avatar Pali Rohár Committed by Lorenzo Pieralisi
Browse files

PCI: aardvark: Fix setting MSI address 

MSI address for receiving MSI interrupts needs to be correctly set before
enabling processing of MSI interrupts.

Move code for setting PCIE_MSI_ADDR_LOW_REG and PCIE_MSI_ADDR_HIGH_REG
from advk_pcie_init_msi_irq_domain() to advk_pcie_setup_hw(), before
enabling PCIE_CORE_CTRL2_MSI_ENABLE.

After this we can remove the now unused member msi_msg, which was used
only for MSI doorbell address. MSI address can be any address which cannot
be used to DMA to. So change it to the address of the main struct advk_pcie.

Link: https://lore.kernel.org/r/20220110015018.26359-12-kabel@kernel.org


Fixes: 8c39d710 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Signed-off-by: default avatarMarek Behún <kabel@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org # f21a8b1b ("PCI: aardvark: Move to MSI handling using generic MSI support")
parent e77d9c90

drivers/pci/controller/pci-aardvark.c

+9 −12
Original line number Diff line number Diff line
@@ -277,7 +277,6 @@ struct advk_pcie { 
	raw_spinlock_t msi_irq_lock;

	DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);

	struct mutex msi_used_lock;

	u16 msi_msg;

	int link_gen;

	struct pci_bridge_emul bridge;

	struct gpio_desc *reset_gpio;
@@ -472,6 +471,7 @@ static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) 


static void advk_pcie_setup_hw(struct advk_pcie *pcie)

{

	phys_addr_t msi_addr;

	u32 reg;

	int i;
@@ -560,6 +560,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) 
	reg |= LANE_COUNT_1;

	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);



	/* Set MSI address */

	msi_addr = virt_to_phys(pcie);

	advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG);

	advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG);



	/* Enable MSI */

	reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);

	reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
@@ -1175,10 +1180,10 @@ static void advk_msi_irq_compose_msi_msg(struct irq_data *data, 
					 struct msi_msg *msg)

{

	struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);

	phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);

	phys_addr_t msi_addr = virt_to_phys(pcie);



	msg->address_lo = lower_32_bits(msi_msg);

	msg->address_hi = upper_32_bits(msi_msg);

	msg->address_lo = lower_32_bits(msi_addr);

	msg->address_hi = upper_32_bits(msi_addr);

	msg->data = data->hwirq;

}
@@ -1337,18 +1342,10 @@ static struct msi_domain_info advk_msi_domain_info = { 
static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)

{

	struct device *dev = &pcie->pdev->dev;

	phys_addr_t msi_msg_phys;



	raw_spin_lock_init(&pcie->msi_irq_lock);

	mutex_init(&pcie->msi_used_lock);



	msi_msg_phys = virt_to_phys(&pcie->msi_msg);



	advk_writel(pcie, lower_32_bits(msi_msg_phys),

		    PCIE_MSI_ADDR_LOW_REG);

	advk_writel(pcie, upper_32_bits(msi_msg_phys),

		    PCIE_MSI_ADDR_HIGH_REG);



	pcie->msi_inner_domain =

		irq_domain_add_linear(NULL, MSI_IRQ_NUM,

				      &advk_msi_domain_ops, pcie);