Commit 48f8f016 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/dg2: Don't wait for AUX power well enable ACKs 



On DG2 we're supposed to just wait 600us after programming the well
before moving on; there won't be an ack from the hardware.

Bspec: 49296
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210721223043.834562-14-matthew.d.roper@intel.com
parent 87fc875a

drivers/gpu/drm/i915/display/intel_display_power.c

+16 −0
Original line number Diff line number Diff line
@@ -341,6 +341,17 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 
{

	const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;

	int pw_idx = power_well->desc->hsw.idx;

	int enable_delay = power_well->desc->hsw.fixed_enable_delay;



	/*

	 * For some power wells we're not supposed to watch the status bit for

	 * an ack, but rather just wait a fixed amount of time and then

	 * proceed.  This is only used on DG2.

	 */

	if (IS_DG2(dev_priv) && enable_delay) {

		usleep_range(enable_delay, 2 * enable_delay);

		return;

	}



	/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */

	if (intel_de_wait_for_set(dev_priv, regs->driver,
@@ -4828,6 +4839,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = { 
		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,

			.hsw.fixed_enable_delay = 600,

		},

	},

	{
@@ -4838,6 +4850,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = { 
		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,

			.hsw.fixed_enable_delay = 600,

		},

	},

	{
@@ -4848,6 +4861,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = { 
		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = ICL_PW_CTL_IDX_AUX_C,

			.hsw.fixed_enable_delay = 600,

		},

	},

	{
@@ -4858,6 +4872,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = { 
		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = XELPD_PW_CTL_IDX_AUX_D,

			.hsw.fixed_enable_delay = 600,

		},

	},

	{
@@ -4878,6 +4893,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = { 
		{

			.hsw.regs = &icl_aux_power_well_regs,

			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,

			.hsw.fixed_enable_delay = 600,

		},

	},

	{

drivers/gpu/drm/i915/display/intel_display_power.h

+6 −0
Original line number Diff line number Diff line
@@ -223,6 +223,12 @@ struct i915_power_well_desc { 
			u8 idx;

			/* Mask of pipes whose IRQ logic is backed by the pw */

			u8 irq_pipe_mask;

			/*

			 * Instead of waiting for the status bit to ack enables,

			 * just wait a specific amount of time and then consider

			 * the well enabled.

			 */

			u16 fixed_enable_delay;

			/* The pw is backing the VGA functionality */

			bool has_vga:1;

			bool has_fuses:1;