Commit 4940b991 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'at91-soc-5.12-2' of... 

Merge tag 'at91-soc-5.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/drivers

AT91 SoC for 5.12 #2

- addition of SAMA7G5 identification to soc.c driver
- enhancements to this soc.c driver

* tag 'at91-soc-5.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  drivers: soc: atmel: add spdx license identifier
  drivers: soc: atmel: add support for sama7g5
  dt-bindings: atmel-sysreg: add "microchip, sama7g5-chipid"
  drivers: soc: atmel: add per soc id and version match masks
  drivers: soc: atmel: fix "__initconst should be placed after socs[]" warning
  drivers: soc: atmel: use GENMASK
  drivers: soc: atmel: add null entry at the end of at91_soc_allowed_list[]
  drivers: soc: atmel: Avoid calling at91_soc_init on non AT91 SoCs

Link: https://lore.kernel.org/r/20210129090030.26976-1-nicolas.ferre@microchip.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7cc623b8 cd9168b4

Documentation/devicetree/bindings/arm/atmel-sysregs.txt

+1 −1
Original line number Diff line number Diff line 
Atmel system registers



Chipid required properties:

- compatible: Should be "atmel,sama5d2-chipid"

- compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"

- reg : Should contain registers location and length



PIT Timer required properties:

drivers/soc/atmel/soc.c

+168 −72
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (C) 2015 Atmel

 *

 * Alexandre Belloni <alexandre.belloni@free-electrons.com

 * Boris Brezillon <boris.brezillon@free-electrons.com

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 *

 */



#define pr_fmt(fmt)	"AT91: " fmt
@@ -25,136 +21,217 @@ 
#define AT91_DBGU_EXID			0x44

#define AT91_CHIPID_CIDR		0x00

#define AT91_CHIPID_EXID		0x04

#define AT91_CIDR_VERSION(x)		((x) & 0x1f)

#define AT91_CIDR_VERSION(x, m)		((x) & (m))

#define AT91_CIDR_VERSION_MASK		GENMASK(4, 0)

#define AT91_CIDR_VERSION_MASK_SAMA7G5	GENMASK(3, 0)

#define AT91_CIDR_EXT			BIT(31)

#define AT91_CIDR_MATCH_MASK		0x7fffffe0

#define AT91_CIDR_MATCH_MASK		GENMASK(30, 5)

#define AT91_CIDR_MASK_SAMA7G5		GENMASK(27, 5)



static const struct at91_soc __initconst socs[] = {

static const struct at91_soc socs[] __initconst = {

#ifdef CONFIG_SOC_AT91RM9200

	AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),

	AT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, 0, "at91rm9200 BGA", "at91rm9200"),

#endif

#ifdef CONFIG_SOC_AT91SAM9

	AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL),

	AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL),

	AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL),

	AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL),

	AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL),

	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,

	AT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, 0, "at91sam9260", NULL),

	AT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, 0, "at91sam9261", NULL),

	AT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, 0, "at91sam9263", NULL),

	AT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, 0, "at91sam9g20", NULL),

	AT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, 0, "at91sam9rl64", NULL),

	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH,

		 "at91sam9m11", "at91sam9g45"),

	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,

	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH,

		 "at91sam9m10", "at91sam9g45"),

	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,

	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH,

		 "at91sam9g46", "at91sam9g45"),

	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,

	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH,

		 "at91sam9g45", "at91sam9g45"),

	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,

	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH,

		 "at91sam9g15", "at91sam9x5"),

	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,

	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH,

		 "at91sam9g35", "at91sam9x5"),

	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,

	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH,

		 "at91sam9x35", "at91sam9x5"),

	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,

	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH,

		 "at91sam9g25", "at91sam9x5"),

	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,

	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH,

		 "at91sam9x25", "at91sam9x5"),

	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,

	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH,

		 "at91sam9cn12", "at91sam9n12"),

	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,

	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH,

		 "at91sam9n12", "at91sam9n12"),

	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,

	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH,

		 "at91sam9cn11", "at91sam9n12"),

	AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),

	AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),

	AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),

	AT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe128", "at91sam9xe128"),

	AT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe256", "at91sam9xe256"),

	AT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe512", "at91sam9xe512"),

#endif

#ifdef CONFIG_SOC_SAM9X60

	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"),

	AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,

		 "sam9x60", "sam9x60"),

	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH,

		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,

		 "sam9x60 64MiB DDR2 SiP", "sam9x60"),

	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH,

		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,

		 "sam9x60 128MiB DDR2 SiP", "sam9x60"),

	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH,

		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,

		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),

#endif

#ifdef CONFIG_SOC_SAMA5

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,

		 "sama5d21", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH,

		 "sama5d22", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D225C_D1M_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH,

		 "sama5d225c 16MiB SiP", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH,

		 "sama5d23", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH,

		 "sama5d24", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH,

		 "sama5d24", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH,

		 "sama5d26", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH,

		 "sama5d27", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH,

		 "sama5d27", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D1G_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH,

		 "sama5d27c 128MiB SiP", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D5M_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH,

		 "sama5d27c 64MiB SiP", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD1G_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH,

		 "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD2G_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH,

		 "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH,

		 "sama5d28", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH,

		 "sama5d28", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_D1G_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH,

		 "sama5d28c 128MiB SiP", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD1G_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH,

		 "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"),

	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD2G_EXID_MATCH,

	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH,

		 "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),

	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,

	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH,

		 "sama5d31", "sama5d3"),

	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,

	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH,

		 "sama5d33", "sama5d3"),

	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,

	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH,

		 "sama5d34", "sama5d3"),

	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,

	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH,

		 "sama5d35", "sama5d3"),

	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,

	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH,

		 "sama5d36", "sama5d3"),

	AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,

	AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH,

		 "sama5d41", "sama5d4"),

	AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,

	AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH,

		 "sama5d42", "sama5d4"),

	AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,

	AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH,

		 "sama5d43", "sama5d4"),

	AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,

	AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH,

		 "sama5d44", "sama5d4"),

#endif

#ifdef CONFIG_SOC_SAMV7

	AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH,

	AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH,

		 "same70q21", "same7"),

	AT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH,

	AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,

		 "same70q20", "same7"),

	AT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH,

	AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK

		 AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,

		 "same70q19", "same7"),

	AT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH,

	AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH,

		 "sams70q21", "sams7"),

	AT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH,

	AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH,

		 "sams70q20", "sams7"),

	AT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH,

	AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH,

		 "sams70q19", "sams7"),

	AT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH,

	AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH,

		 "samv71q21", "samv7"),

	AT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH,

	AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH,

		 "samv71q20", "samv7"),

	AT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH,

	AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH,

		 "samv71q19", "samv7"),

	AT91_SOC(SAMV70Q20_CIDR_MATCH, SAMV70Q20_EXID_MATCH,

	AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH,

		 "samv70q20", "samv7"),

	AT91_SOC(SAMV70Q19_CIDR_MATCH, SAMV70Q19_EXID_MATCH,

	AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,

		 "samv70q19", "samv7"),

#endif

#ifdef CONFIG_SOC_SAMA7

	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH,

		 "sama7g51", "sama7g5"),

	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH,

		 "sama7g52", "sama7g5"),

	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH,

		 "sama7g53", "sama7g5"),

	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,

		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH,

		 "sama7g54", "sama7g5"),

#endif

	{ /* sentinel */ },

};
@@ -191,8 +268,13 @@ static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid) 
{

	struct device_node *np;

	void __iomem *regs;

	static const struct of_device_id chipids[] = {

		{ .compatible = "atmel,sama5d2-chipid" },

		{ .compatible = "microchip,sama7g5-chipid" },

		{ },

	};



	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid");

	np = of_find_matching_node(NULL, chipids);

	if (!np)

		return -ENODEV;
@@ -235,7 +317,7 @@ struct soc_device * __init at91_soc_init(const struct at91_soc *socs) 
	}



	for (soc = socs; soc->name; soc++) {

		if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK))

		if (soc->cidr_match != (cidr & soc->cidr_mask))

			continue;



		if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
@@ -254,7 +336,7 @@ struct soc_device * __init at91_soc_init(const struct at91_soc *socs) 
	soc_dev_attr->family = soc->family;

	soc_dev_attr->soc_id = soc->name;

	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",

					   AT91_CIDR_VERSION(cidr));

					   AT91_CIDR_VERSION(cidr, soc->version_mask));

	soc_dev = soc_device_register(soc_dev_attr);

	if (IS_ERR(soc_dev)) {

		kfree(soc_dev_attr->revision);
@@ -266,13 +348,27 @@ struct soc_device * __init at91_soc_init(const struct at91_soc *socs) 
	if (soc->family)

		pr_info("Detected SoC family: %s\n", soc->family);

	pr_info("Detected SoC: %s, revision %X\n", soc->name,

		AT91_CIDR_VERSION(cidr));

		AT91_CIDR_VERSION(cidr, soc->version_mask));



	return soc_dev;

}



static const struct of_device_id at91_soc_allowed_list[] __initconst = {

	{ .compatible = "atmel,at91rm9200", },

	{ .compatible = "atmel,at91sam9", },

	{ .compatible = "atmel,sama5", },

	{ .compatible = "atmel,samv7", },

	{ .compatible = "microchip,sama7g5", },

	{ }

};



static int __init atmel_soc_device_init(void)

{

	struct device_node *np = of_find_node_by_path("/");



	if (!of_match_node(at91_soc_allowed_list, np))

		return 0;



	at91_soc_init(socs);



	return 0;

drivers/soc/atmel/soc.h

+13 −6
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (C) 2015 Atmel

 *

 * Boris Brezillon <boris.brezillon@free-electrons.com

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 *

 */



#ifndef __AT91_SOC_H
@@ -16,14 +12,19 @@ 


struct at91_soc {

	u32 cidr_match;

	u32 cidr_mask;

	u32 version_mask;

	u32 exid_match;

	const char *name;

	const char *family;

};



#define AT91_SOC(__cidr, __exid, __name, __family)		\

#define AT91_SOC(__cidr, __cidr_mask, __version_mask, __exid,	\

		 __name, __family)				\

	{							\

		.cidr_match = (__cidr),				\

		.cidr_mask = (__cidr_mask),			\

		.version_mask = (__version_mask),		\

		.exid_match = (__exid),				\

		.name = (__name),				\

		.family = (__family),				\
@@ -43,6 +44,7 @@ at91_soc_init(const struct at91_soc *socs); 
#define AT91SAM9X5_CIDR_MATCH		0x019a05a0

#define AT91SAM9N12_CIDR_MATCH		0x019a07a0

#define SAM9X60_CIDR_MATCH		0x019b35a0

#define SAMA7G5_CIDR_MATCH		0x00162100



#define AT91SAM9M11_EXID_MATCH		0x00000001

#define AT91SAM9M10_EXID_MATCH		0x00000002
@@ -64,6 +66,11 @@ at91_soc_init(const struct at91_soc *socs); 
#define SAM9X60_D1G_EXID_MATCH		0x00000010

#define SAM9X60_D6K_EXID_MATCH		0x00000011



#define SAMA7G51_EXID_MATCH		0x3

#define SAMA7G52_EXID_MATCH		0x2

#define SAMA7G53_EXID_MATCH		0x1

#define SAMA7G54_EXID_MATCH		0x0



#define AT91SAM9XE128_CIDR_MATCH	0x329973a0

#define AT91SAM9XE256_CIDR_MATCH	0x329a93a0

#define AT91SAM9XE512_CIDR_MATCH	0x329aa3a0