Commit 49e46976 authored by Kuninori Morimoto's avatar Kuninori Morimoto Committed by Geert Uytterhoeven
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pinctrl: renesas: r8a779g0: Add missing SCIF3 



R-Car V4H has SCIF3 and SCIF3_A, but current PFC setting is mixed.
This patch cleans up SCIF3/SCIF3_A, based on Rev.0.51.

Signed-off-by: default avatarKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87v8shsja7.wl-kuninori.morimoto.gx@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent cf4f7891

drivers/pinctrl/renesas/pfc-r8a779g0.c

+53 −18
Original line number Diff line number Diff line
@@ -295,11 +295,11 @@ 


/* SR1 */

/* IP0SR1 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */

#define IP0SR1_3_0	FM(MSIOF1_SS2)		FM(HTX3_A)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR1_7_4	FM(MSIOF1_SS1)		FM(HCTS3_N_A)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR1_11_8	FM(MSIOF1_SYNC)		FM(HRTS3_N_A)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR1_15_12	FM(MSIOF1_SCK)		FM(HSCK3_A)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR1_19_16	FM(MSIOF1_TXD)		FM(HRX3_A)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR1_3_0	FM(MSIOF1_SS2)		FM(HTX3_A)		FM(TX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR1_7_4	FM(MSIOF1_SS1)		FM(HCTS3_N_A)		FM(RX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR1_11_8	FM(MSIOF1_SYNC)		FM(HRTS3_N_A)		FM(RTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR1_15_12	FM(MSIOF1_SCK)		FM(HSCK3_A)		FM(CTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR1_19_16	FM(MSIOF1_TXD)		FM(HRX3_A)		FM(SCK3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR1_23_20	FM(MSIOF1_RXD)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR1_27_24	FM(MSIOF0_SS2)		FM(HTX1_X)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR1_31_28	FM(MSIOF0_SS1)		FM(HRX1_X)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -325,11 +325,11 @@ 
#define IP2SR1_31_28	F_(0, 0)		FM(TCLK2)		FM(MSIOF4_SS1)	FM(IRQ3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)



/* IP3SR1 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */

#define IP3SR1_3_0	FM(HRX3)		FM(SCK3)		FM(MSIOF4_SS2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP3SR1_7_4	FM(HSCK3)		FM(CTS3_N)		FM(MSIOF4_SCK)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP3SR1_11_8	FM(HRTS3_N)		FM(RTS3_N)		FM(MSIOF4_TXD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP3SR1_15_12	FM(HCTS3_N)		FM(RX3)			FM(MSIOF4_RXD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP3SR1_19_16	FM(HTX3)		FM(TX3)			FM(MSIOF4_SYNC)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP3SR1_3_0	FM(HRX3)		FM(SCK3_A)		FM(MSIOF4_SS2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP3SR1_7_4	FM(HSCK3)		FM(CTS3_N_A)		FM(MSIOF4_SCK)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP3SR1_11_8	FM(HRTS3_N)		FM(RTS3_N_A)		FM(MSIOF4_TXD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP3SR1_15_12	FM(HCTS3_N)		FM(RX3_A)		FM(MSIOF4_RXD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP3SR1_19_16	FM(HTX3)		FM(TX3_A)		FM(MSIOF4_SYNC)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)



/* SR2 */

/* IP0SR2 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
@@ -795,18 +795,23 @@ static const u16 pinmux_data[] = { 
	/* IP0SR1 */

	PINMUX_IPSR_GPSR(IP0SR1_3_0,	MSIOF1_SS2),

	PINMUX_IPSR_GPSR(IP0SR1_3_0,	HTX3_A),

	PINMUX_IPSR_GPSR(IP0SR1_3_0,	TX3),



	PINMUX_IPSR_GPSR(IP0SR1_7_4,	MSIOF1_SS1),

	PINMUX_IPSR_GPSR(IP0SR1_7_4,	HCTS3_N_A),

	PINMUX_IPSR_GPSR(IP0SR1_7_4,	RX3),



	PINMUX_IPSR_GPSR(IP0SR1_11_8,	MSIOF1_SYNC),

	PINMUX_IPSR_GPSR(IP0SR1_11_8,	HRTS3_N_A),

	PINMUX_IPSR_GPSR(IP0SR1_11_8,	RTS3_N),



	PINMUX_IPSR_GPSR(IP0SR1_15_12,	MSIOF1_SCK),

	PINMUX_IPSR_GPSR(IP0SR1_15_12,	HSCK3_A),

	PINMUX_IPSR_GPSR(IP0SR1_15_12,	CTS3_N),



	PINMUX_IPSR_GPSR(IP0SR1_19_16,	MSIOF1_TXD),

	PINMUX_IPSR_GPSR(IP0SR1_19_16,	HRX3_A),

	PINMUX_IPSR_GPSR(IP0SR1_19_16,	SCK3),



	PINMUX_IPSR_GPSR(IP0SR1_23_20,	MSIOF1_RXD),
@@ -871,23 +876,23 @@ static const u16 pinmux_data[] = { 


	/* IP3SR1 */

	PINMUX_IPSR_GPSR(IP3SR1_3_0,	HRX3),

	PINMUX_IPSR_GPSR(IP3SR1_3_0,	SCK3),

	PINMUX_IPSR_GPSR(IP3SR1_3_0,	SCK3_A),

	PINMUX_IPSR_GPSR(IP3SR1_3_0,	MSIOF4_SS2),



	PINMUX_IPSR_GPSR(IP3SR1_7_4,	HSCK3),

	PINMUX_IPSR_GPSR(IP3SR1_7_4,	CTS3_N),

	PINMUX_IPSR_GPSR(IP3SR1_7_4,	CTS3_N_A),

	PINMUX_IPSR_GPSR(IP3SR1_7_4,	MSIOF4_SCK),



	PINMUX_IPSR_GPSR(IP3SR1_11_8,	HRTS3_N),

	PINMUX_IPSR_GPSR(IP3SR1_11_8,	RTS3_N),

	PINMUX_IPSR_GPSR(IP3SR1_11_8,	RTS3_N_A),

	PINMUX_IPSR_GPSR(IP3SR1_11_8,	MSIOF4_TXD),



	PINMUX_IPSR_GPSR(IP3SR1_15_12,	HCTS3_N),

	PINMUX_IPSR_GPSR(IP3SR1_15_12,	RX3),

	PINMUX_IPSR_GPSR(IP3SR1_15_12,	RX3_A),

	PINMUX_IPSR_GPSR(IP3SR1_15_12,	MSIOF4_RXD),



	PINMUX_IPSR_GPSR(IP3SR1_19_16,	HTX3),

	PINMUX_IPSR_GPSR(IP3SR1_19_16,	TX3),

	PINMUX_IPSR_GPSR(IP3SR1_19_16,	TX3_A),

	PINMUX_IPSR_GPSR(IP3SR1_19_16,	MSIOF4_SYNC),



	/* IP0SR2 */
@@ -2198,6 +2203,29 @@ static const unsigned int scif3_ctrl_mux[] = { 
	RTS3_N_MARK, CTS3_N_MARK,

};



/* - SCIF3_A ------------------------------------------------------------------ */

static const unsigned int scif3_data_a_pins[] = {

	/* RX3_A, TX3_A */

	RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),

};

static const unsigned int scif3_data_a_mux[] = {

	RX3_A_MARK, TX3_A_MARK,

};

static const unsigned int scif3_clk_a_pins[] = {

	/* SCK3_A */

	RCAR_GP_PIN(1, 24),

};

static const unsigned int scif3_clk_a_mux[] = {

	SCK3_A_MARK,

};

static const unsigned int scif3_ctrl_a_pins[] = {

	/* RTS3_N_A, CTS3_N_A */

	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),

};

static const unsigned int scif3_ctrl_a_mux[] = {

	RTS3_N_A_MARK, CTS3_N_A_MARK,

};



/* - SCIF4 ------------------------------------------------------------------ */

static const unsigned int scif4_data_pins[] = {

	/* RX4, TX4 */
@@ -2475,9 +2503,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { 
	SH_PFC_PIN_GROUP(scif1_data),

	SH_PFC_PIN_GROUP(scif1_clk),

	SH_PFC_PIN_GROUP(scif1_ctrl),

	SH_PFC_PIN_GROUP(scif3_data),

	SH_PFC_PIN_GROUP(scif3_clk),

	SH_PFC_PIN_GROUP(scif3_ctrl),

	SH_PFC_PIN_GROUP(scif3_data),		/* suffix might be updated */

	SH_PFC_PIN_GROUP(scif3_clk),		/* suffix might be updated */

	SH_PFC_PIN_GROUP(scif3_ctrl),		/* suffix might be updated */

	SH_PFC_PIN_GROUP(scif3_data_a),		/* suffix might be updated */

	SH_PFC_PIN_GROUP(scif3_clk_a),		/* suffix might be updated */

	SH_PFC_PIN_GROUP(scif3_ctrl_a),		/* suffix might be updated */

	SH_PFC_PIN_GROUP(scif4_data),

	SH_PFC_PIN_GROUP(scif4_clk),

	SH_PFC_PIN_GROUP(scif4_ctrl),
@@ -2760,9 +2791,13 @@ static const char * const scif1_groups[] = { 
};



static const char * const scif3_groups[] = {

	/* suffix might be updated */

	"scif3_data",

	"scif3_clk",

	"scif3_ctrl",

	"scif3_data_a",

	"scif3_clk_a",

	"scif3_ctrl_a",

};



static const char * const scif4_groups[] = {