Commit 49fd30a7 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dsi: use DRM DSC helpers for DSC setup 



Use new DRM DSC helpers to setup DSI DSC configuration. The
initial_scale_value needs to be adjusted according to the standard, but
this is a separate change.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: default avatarJessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/539276/
Link: https://lore.kernel.org/r/20230329-rfc-msm-dsc-helper-v14-4-bafc7be95691@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 68858328

drivers/gpu/drm/msm/dsi/dsi_host.c

+8 −53
Original line number Diff line number Diff line
@@ -1728,28 +1728,9 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 
	return -EINVAL;

}



static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {

	0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,

	0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e

};



/* only 8bpc, 8bpp added */

static char min_qp[DSC_NUM_BUF_RANGES] = {

	0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13

};



static char max_qp[DSC_NUM_BUF_RANGES] = {

	4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15

};



static char bpg_offset[DSC_NUM_BUF_RANGES] = {

	2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12

};



static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)

{

	int i;

	u16 bpp = dsc->bits_per_pixel >> 4;

	int ret;



	if (dsc->bits_per_pixel & 0xf) {

		DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
@@ -1761,49 +1742,23 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc 
		return -EOPNOTSUPP;

	}



	dsc->rc_model_size = 8192;

	dsc->first_line_bpg_offset = 12;

	dsc->rc_edge_factor = 6;

	dsc->rc_tgt_offset_high = 3;

	dsc->rc_tgt_offset_low = 3;

	dsc->simple_422 = 0;

	dsc->convert_rgb = 1;

	dsc->vbr_enable = 0;



	/* handle only bpp = bpc = 8 */

	for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)

		dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];

	drm_dsc_set_const_params(dsc);

	drm_dsc_set_rc_buf_thresh(dsc);



	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {

		dsc->rc_range_params[i].range_min_qp = min_qp[i];

		dsc->rc_range_params[i].range_max_qp = max_qp[i];

		/*

		 * Range BPG Offset contains two's-complement signed values that fill

		 * 8 bits, yet the registers and DCS PPS field are only 6 bits wide.

		 */

		dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK;

	/* handle only bpp = bpc = 8, pre-SCR panels */

	ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR);

	if (ret) {

		DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n");

		return ret;

	}



	dsc->initial_offset = 6144;		/* Not bpp 12 */

	if (bpp != 8)

		dsc->initial_offset = 2048;	/* bpp = 12 */



	if (dsc->bits_per_component <= 10)

		dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;

	else

		dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;



	dsc->initial_xmit_delay = 512;

	dsc->initial_scale_value = 32;

	dsc->first_line_bpg_offset = 12;

	dsc->line_buf_depth = dsc->bits_per_component + 1;



	/* bpc 8 */

	dsc->flatness_min_qp = 3;

	dsc->flatness_max_qp = 12;

	dsc->rc_quant_incr_limit0 = 11;

	dsc->rc_quant_incr_limit1 = 11;



	return drm_dsc_compute_rc_parameters(dsc);

}