Commit 4bc500ef authored by James Clark's avatar James Clark Committed by Mathieu Poirier
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coresight: etm3x: Cleanup ETMTECR1 register accesses 



This is a no-op change for style and consistency and has no effect on
the binary output by the compiler. These fields already have macros
to define them so use them instead of magic numbers.

Signed-off-by: default avatarJames Clark <james.clark@arm.com>
Reviewed-by: default avatarMike Leach <mike.leach@linaro.org>
Link: https://lore.kernel.org/r/20220304171913.2292458-11-james.clark@arm.com


Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
parent 6ba7f2bc

drivers/hwtracing/coresight/coresight-etm3x-core.c

+1 −1
Original line number Diff line number Diff line
@@ -204,7 +204,7 @@ void etm_set_default(struct etm_config *config) 
	 *  set all bits in register 0x007, the ETMTECR2, to 0

	 *  set register 0x008, the ETMTEEVR, to 0x6F (TRUE).

	 */

	config->enable_ctrl1 = BIT(24);

	config->enable_ctrl1 = ETMTECR1_INC_EXC;

	config->enable_ctrl2 = 0x0;

	config->enable_event = ETM_HARD_WIRE_RES_A;

drivers/hwtracing/coresight/coresight-etm3x-sysfs.c

+1 −1
Original line number Diff line number Diff line
@@ -474,7 +474,7 @@ static ssize_t addr_start_store(struct device *dev, 
	config->addr_val[idx] = val;

	config->addr_type[idx] = ETM_ADDR_TYPE_START;

	config->startstop_ctrl |= (1 << idx);

	config->enable_ctrl1 |= BIT(25);

	config->enable_ctrl1 |= ETMTECR1_START_STOP;

	spin_unlock(&drvdata->spinlock);



	return size;