Commit 4c85e20b authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Stephen Boyd
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clk: mediatek: Consistently use GATE_MTK() macro 



All the various MediaTek clock drivers are, in a way or another,
redefining the GATE_MTK() macro with different names: while some
are doing that by actually using GATE_MTK(), others are copying
it entirely (hence, entirely redefining it).

Change all clock drivers to always and consistently use this macro.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-23-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 3f37ba7c

drivers/clk/mediatek/clk-mt2701-aud.c

+8 −32
Original line number Diff line number Diff line
@@ -15,41 +15,17 @@ 


#include <dt-bindings/clock/mt2701-clk.h>



#define GATE_AUDIO0(_id, _name, _parent, _shift) {	\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &audio0_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_no_setclr,	\

	}

#define GATE_AUDIO0(_id, _name, _parent, _shift)		\

	GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)



#define GATE_AUDIO1(_id, _name, _parent, _shift) {	\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &audio1_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_no_setclr,	\

	}

#define GATE_AUDIO1(_id, _name, _parent, _shift)		\

	GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)



#define GATE_AUDIO2(_id, _name, _parent, _shift) {	\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &audio2_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_no_setclr,	\

	}

#define GATE_AUDIO2(_id, _name, _parent, _shift)		\

	GATE_MTK(_id, _name, _parent, &audio2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)



#define GATE_AUDIO3(_id, _name, _parent, _shift) {	\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &audio3_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_no_setclr,	\

	}

#define GATE_AUDIO3(_id, _name, _parent, _shift)		\

	GATE_MTK(_id, _name, _parent, &audio3_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)



static const struct mtk_gate_regs audio0_cg_regs = {

	.set_ofs = 0x0,

drivers/clk/mediatek/clk-mt2701-bdp.c

+4 −16
Original line number Diff line number Diff line
@@ -24,23 +24,11 @@ static const struct mtk_gate_regs bdp1_cg_regs = { 
	.sta_ofs = 0x0110,

};



#define GATE_BDP0(_id, _name, _parent, _shift) {	\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &bdp0_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_setclr_inv,	\

	}

#define GATE_BDP0(_id, _name, _parent, _shift)			\

	GATE_MTK(_id, _name, _parent, &bdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)



#define GATE_BDP1(_id, _name, _parent, _shift) {	\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &bdp1_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_setclr_inv,	\

	}

#define GATE_BDP1(_id, _name, _parent, _shift)			\

	GATE_MTK(_id, _name, _parent, &bdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)



static const struct mtk_gate bdp_clks[] = {

	GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),

drivers/clk/mediatek/clk-mt2701-eth.c

+2 −8
Original line number Diff line number Diff line
@@ -16,14 +16,8 @@ static const struct mtk_gate_regs eth_cg_regs = { 
	.sta_ofs = 0x0030,

};



#define GATE_ETH(_id, _name, _parent, _shift) {		\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &eth_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\

	}

#define GATE_ETH(_id, _name, _parent, _shift)			\

	GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)



static const struct mtk_gate eth_clks[] = {

	GATE_DUMMY(CLK_DUMMY, "eth_dummy"),

drivers/clk/mediatek/clk-mt2701-g3d.c

+2 −8
Original line number Diff line number Diff line
@@ -16,14 +16,8 @@ 


#include <dt-bindings/clock/mt2701-clk.h>



#define GATE_G3D(_id, _name, _parent, _shift) {	\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &g3d_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_setclr,	\

	}

#define GATE_G3D(_id, _name, _parent, _shift)				\

	GATE_MTK(_id, _name, _parent, &g3d_cg_regs, _shift, &mtk_clk_gate_ops_setclr)



static const struct mtk_gate_regs g3d_cg_regs = {

	.sta_ofs = 0x0,

drivers/clk/mediatek/clk-mt2701-hif.c

+2 −8
Original line number Diff line number Diff line
@@ -16,14 +16,8 @@ static const struct mtk_gate_regs hif_cg_regs = { 
	.sta_ofs = 0x0030,

};



#define GATE_HIF(_id, _name, _parent, _shift) {		\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &hif_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\

	}

#define GATE_HIF(_id, _name, _parent, _shift)				\

	GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)



static const struct mtk_gate hif_clks[] = {

	GATE_DUMMY(CLK_DUMMY, "hif_dummy"),