Commit 4dd25272 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Update metrics for Haswell 

Based on TMA_metrics-full.csv version 4.3 at 01.org:
    https://download.01.org/perfmon/
Events are updated to version 30:
    https://download.01.org/perfmon/HSW
Json files generated by the latest code at:
    https://github.com/intel/event-converter-for-linux-perf



Tested:

Not tested on a Haswell, on a SkylakeX:

  ...
    9: Parse perf pmu format                                           : Ok
   10: PMU events                                                      :
   10.1: PMU event table sanity                                        : Ok
   10.2: PMU event map aliases                                         : Ok
   10.3: Parsing of PMU event table metrics                            : Ok
   10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
  ...

Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220201015858.1226914-15-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 45957c1e

tools/perf/pmu-events/arch/x86/haswell/cache.json

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tools/perf/pmu-events/arch/x86/haswell/floating-point.json

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[

    {

        "PEBS": "1",

        "PublicDescription": "",

        "EventCode": "0xC1",

        "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",

        "Counter": "0,1,2,3",

        "UMask": "0x8",

        "Errata": "HSD56, HSM57",

        "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

        "SampleAfterValue": "100003",

        "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC6",

        "EventName": "AVX_INSTS.ALL",

        "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",

        "SampleAfterValue": "2000003",

        "UMask": "0x7"

    },

    {

        "PEBS": "1",

        "PublicDescription": "",

        "EventCode": "0xC1",

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "Counter": "0,1,2,3",

        "UMask": "0x10",

        "Errata": "HSD56, HSM57",

        "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

        "CounterHTOff": "0,1,2,3",

        "CounterMask": "1",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.ANY",

        "PublicDescription": "Cycles with any input/output SSE* or FP assists.",

        "SampleAfterValue": "100003",

        "BriefDescription": "Number of transitions from legacy SSE to AVX-256 when penalty applicable",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x1e"

    },

    {

        "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",

        "EventCode": "0xC6",

        "BriefDescription": "Number of SIMD FP assists due to input values",

        "Counter": "0,1,2,3",

        "UMask": "0x7",

        "EventName": "AVX_INSTS.ALL",

        "SampleAfterValue": "2000003",

        "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.SIMD_INPUT",

        "PublicDescription": "Number of SIMD FP assists due to input values.",

        "SampleAfterValue": "100003",

        "UMask": "0x10"

    },

    {

        "PEBS": "1",

        "PublicDescription": "",

        "EventCode": "0xCA",

        "BriefDescription": "Number of SIMD FP assists due to Output values",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "EventName": "FP_ASSIST.X87_OUTPUT",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.SIMD_OUTPUT",

        "PublicDescription": "Number of SIMD FP assists due to output values.",

        "SampleAfterValue": "100003",

        "BriefDescription": "output - Numeric Overflow, Numeric Underflow, Inexact Result",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x8"

    },

    {

        "PEBS": "1",

        "PublicDescription": "",

        "EventCode": "0xCA",

        "BriefDescription": "Number of X87 assists due to input value.",

        "Counter": "0,1,2,3",

        "UMask": "0x4",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.X87_INPUT",

        "PublicDescription": "Number of X87 FP assists due to input values.",

        "SampleAfterValue": "100003",

        "BriefDescription": "input - Invalid Operation, Denormal Operand, SNaN Operand",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x4"

    },

    {

        "PEBS": "1",

        "PublicDescription": "",

        "EventCode": "0xCA",

        "BriefDescription": "Number of X87 assists due to output value.",

        "Counter": "0,1,2,3",

        "UMask": "0x8",

        "EventName": "FP_ASSIST.SIMD_OUTPUT",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xCA",

        "EventName": "FP_ASSIST.X87_OUTPUT",

        "PublicDescription": "Number of X87 FP assists due to output values.",

        "SampleAfterValue": "100003",

        "BriefDescription": "SSE* FP micro-code assist when output value is invalid.",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x2"

    },

    {

        "PEBS": "1",

        "PublicDescription": "",

        "EventCode": "0xCA",

        "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",

        "Counter": "0,1,2,3",

        "UMask": "0x10",

        "EventName": "FP_ASSIST.SIMD_INPUT",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x58",

        "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",

        "PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.",

        "SampleAfterValue": "1000003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x58",

        "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",

        "PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.",

        "SampleAfterValue": "1000003",

        "UMask": "0x8"

    },

    {

        "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "Errata": "HSD56, HSM57",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.AVX_TO_SSE",

        "SampleAfterValue": "100003",

        "BriefDescription": "Any input SSE* FP Assist",

        "CounterHTOff": "0,1,2,3,4,5,6,7"

        "UMask": "0x8"

    },

    {

        "PEBS": "1",

        "PublicDescription": "",

        "EventCode": "0xCA",

        "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",

        "Counter": "0,1,2,3",

        "UMask": "0x1e",

        "EventName": "FP_ASSIST.ANY",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "Errata": "HSD56, HSM57",

        "EventCode": "0xC1",

        "EventName": "OTHER_ASSISTS.SSE_TO_AVX",

        "SampleAfterValue": "100003",

        "BriefDescription": "Counts any FP_ASSIST umask was incrementing",

        "CounterMask": "1",

        "CounterHTOff": "0,1,2,3"

        "UMask": "0x10"

    }

]
 
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tools/perf/pmu-events/arch/x86/haswell/frontend.json

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tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json

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tools/perf/pmu-events/arch/x86/haswell/memory.json

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