Commit 4decb918 authored by Pali Rohár's avatar Pali Rohár Committed by Viresh Kumar
Browse files

clk: mvebu: armada-37xx-periph: Fix switching CPU freq from 250 Mhz to 1 GHz 



It was observed that the workaround introduced by commit 61c40f35
("clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to
1.2GHz") when base CPU frequency is 1.2 GHz is also required when base
CPU frequency is 1 GHz. Otherwise switching CPU frequency directly from
L2 (250 MHz) to L0 (1 GHz) causes a crash.

When base CPU frequency is just 800 MHz no crashed were observed during
switch from L2 to L0.

Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Acked-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
Tested-by: default avatarTomasz Maciej Nowak <tmn505@gmail.com>
Tested-by: default avatarAnders Trier Olesen <anders.trier.olesen@gmail.com>
Tested-by: default avatarPhilip Soares <philips@netisense.com>
Fixes: 2089dc33 ("clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks")
Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
parent d118ac20

drivers/clk/mvebu/armada-37xx-periph.c

+7 −5
Original line number Diff line number Diff line
@@ -487,8 +487,10 @@ static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate, 
}



/*

 * Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz

 * respectively) to L0 frequency (1.2 Ghz) requires a significant

 * Workaround when base CPU frequnecy is 1000 or 1200 MHz

 *

 * Switching the CPU from the L2 or L3 frequencies (250/300 or 200 MHz

 * respectively) to L0 frequency (1/1.2 GHz) requires a significant

 * amount of time to let VDD stabilize to the appropriate

 * voltage. This amount of time is large enough that it cannot be

 * covered by the hardware countdown register. Due to this, the CPU
@@ -498,15 +500,15 @@ static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate, 
 * To work around this problem, we prevent switching directly from the

 * L2/L3 frequencies to the L0 frequency, and instead switch to the L1

 * frequency in-between. The sequence therefore becomes:

 * 1. First switch from L2/L3(200/300MHz) to L1(600MHZ)

 * 1. First switch from L2/L3 (200/250/300 MHz) to L1 (500/600 MHz)

 * 2. Sleep 20ms for stabling VDD voltage

 * 3. Then switch from L1(600MHZ) to L0(1200Mhz).

 * 3. Then switch from L1 (500/600 MHz) to L0 (1000/1200 MHz).

 */

static void clk_pm_cpu_set_rate_wa(unsigned long rate, struct regmap *base)

{

	unsigned int cur_level;



	if (rate != 1200 * 1000 * 1000)

	if (rate < 1000 * 1000 * 1000)

		return;



	regmap_read(base, ARMADA_37XX_NB_CPU_LOAD, &cur_level);