Commit 4fef0565 authored by Lucas Tanure's avatar Lucas Tanure Committed by Neil Armstrong
Browse files

arm64: dts: amlogic-t7-a311d2-khadas-vim4: add initial device-tree 



The Khadas VIM4 uses the Amlogic A311D2 SoC, based on the Amlogic T7 SoC
family, on a board with the same form factor as the VIM3 models.

- 8GB LPDDR4X 2016MHz
- 32GB eMMC 5.1 storage
- 32MB SPI flash
- 10/100/1000 Base-T Ethernet
- AP6275S Wireless (802.11 a/b/g/n/ac/ax, BT5.1)
- HDMI 2.1 video
- HDMI Input
- 1x USB 2.0 + 1x USB 3.0 ports
- 1x USB-C (power) with USB 2.0 OTG
- 3x LED's (1x red, 1x blue, 1x white)
- 3x buttons (power, function, reset)
- M2 socket with PCIe, USB, ADC & I2C
- 40pin GPIO Header
- 1x micro SD card slot

Signed-off-by: default avatarLucas Tanure <tanure@linux.com>
Link: https://lore.kernel.org/r/20230629073419.207886-5-tanure@linux.com


Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
parent 76ccc468

arch/arm64/boot/dts/amlogic/Makefile

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# SPDX-License-Identifier: GPL-2.0

dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb

dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb

dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb

dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb

dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb

arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright (c) 2022 Wesion, Inc. All rights reserved.

 */



/dts-v1/;



#include "amlogic-t7.dtsi"



/ {

	model = "Khadas vim4";

	compatible = "khadas,vim4", "amlogic,a311d2", "amlogic,t7";



	aliases {

		serial0 = &uart_a;

	};



	memory@0 {

		device_type = "memory";

		reg = <0x0 0x0 0x2 0x0>; /* 8 GB */

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		/* 3 MiB reserved for ARM Trusted Firmware (BL31) */

		secmon_reserved: secmon@5000000 {

			reg = <0x0 0x05000000 0x0 0x300000>;

			no-map;

		};



		/* 32 MiB reserved for ARM Trusted Firmware (BL32) */

		secmon_reserved_bl32: secmon@5300000 {

			reg = <0x0 0x05300000 0x0 0x2000000>;

			no-map;

		};

	};



	xtal: xtal-clk {

		compatible = "fixed-clock";

		clock-frequency = <24000000>;

		clock-output-names = "xtal";

		#clock-cells = <0>;

	};



};



&uart_a {

	status = "okay";

	clocks = <&xtal>, <&xtal>, <&xtal>;

	clock-names = "xtal", "pclk", "baud";

};

arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	cpus {

		#address-cells = <0x2>;

		#size-cells = <0x0>;



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&cpu100>;

				};

				core1 {

					cpu = <&cpu101>;

				};

				core2 {

					cpu = <&cpu102>;

				};

				core3 {

					cpu = <&cpu103>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&cpu0>;

				};

				core1 {

					cpu = <&cpu1>;

				};

				core2 {

					cpu = <&cpu2>;

				};

				core3 {

					cpu = <&cpu3>;

				};

			};

		};



		cpu100: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x100>;

			enable-method = "psci";

		};



		cpu101: cpu@101{

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x101>;

			enable-method = "psci";

		};



		cpu102: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x102>;

			enable-method = "psci";

		};



		cpu103: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x103>;

			enable-method = "psci";

		};



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a73";

			reg = <0x0 0x0>;

			enable-method = "psci";

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a73";

			reg = <0x0 0x1>;

			enable-method = "psci";

		};



		cpu2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a73";

			reg = <0x0 0x2>;

			enable-method = "psci";

		};



		cpu3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a73";

			reg = <0x0 0x3>;

			enable-method = "psci";

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	sm: secure-monitor {

		compatible = "amlogic,meson-gxbb-sm";

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		gic: interrupt-controller@fff01000 {

			compatible = "arm,gic-400";

			#interrupt-cells = <3>;

			#address-cells = <0>;

			interrupt-controller;

			reg = <0x0 0xfff01000 0 0x1000>,

			      <0x0 0xfff02000 0 0x0100>;

			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;

		};



		apb4: bus@fe000000 {

			compatible = "simple-bus";

			reg = <0x0 0xfe000000 0x0 0x480000>;

			#address-cells = <2>;

			#size-cells = <2>;

			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;



			uart_a: serial@78000 {

				compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";

				reg = <0x0 0x78000 0x0 0x18>;

				interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;

				status = "disabled";

			};

		};



	};

};