Commit 52b3dc55 authored by James Morse's avatar James Morse Committed by Will Deacon
Browse files

arm64/sysreg: Standardise naming for ID_ISAR0_EL1 



To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.

Ensure symbols for the ID_ISAR0_EL1 register have an _EL1 suffix,
and use lower-case for feature names where the arm-arm does the same.

To functional change.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-5-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 7b24177c

arch/arm64/include/asm/sysreg.h

+7 −7
Original line number Diff line number Diff line
@@ -710,13 +710,13 @@ 


#define ID_DFR1_MTPMU_SHIFT		0



#define ID_ISAR0_DIVIDE_SHIFT		24

#define ID_ISAR0_DEBUG_SHIFT		20

#define ID_ISAR0_COPROC_SHIFT		16

#define ID_ISAR0_CMPBRANCH_SHIFT	12

#define ID_ISAR0_BITFIELD_SHIFT		8

#define ID_ISAR0_BITCOUNT_SHIFT		4

#define ID_ISAR0_SWAP_SHIFT		0

#define ID_ISAR0_EL1_Divide_SHIFT	24

#define ID_ISAR0_EL1_Debug_SHIFT	20

#define ID_ISAR0_EL1_Coproc_SHIFT	16

#define ID_ISAR0_EL1_CmpBranch_SHIFT	12

#define ID_ISAR0_EL1_BitField_SHIFT	8

#define ID_ISAR0_EL1_BitCount_SHIFT	4

#define ID_ISAR0_EL1_Swap_SHIFT		0



#define ID_ISAR5_RDM_SHIFT		24

#define ID_ISAR5_CRC32_SHIFT		16

arch/arm64/kernel/cpufeature.c

+7 −7
Original line number Diff line number Diff line
@@ -470,13 +470,13 @@ static const struct arm64_ftr_bits ftr_gmid[] = { 
};



static const struct arm64_ftr_bits ftr_id_isar0[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0),

	ARM64_FTR_END,

};