Commit 53442e1c authored by Mike Frysinger's avatar Mike Frysinger Committed by Bryan Wu
Browse files

Blackfin arch: delay PLL_CTL/VR_CTL wrappers 



Delay PLL_CTL/VR_CTL wrappers as much as possible to avoid
the inter-dependency problems with cdef and common headers

Signed-off-by: default avatarMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent b94919e2

arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h

+53 −49
Original line number Diff line number Diff line
@@ -31,7 +31,6 @@ 
#ifndef _CDEF_BF52X_H

#define _CDEF_BF52X_H



#include <asm/system.h>

#include <asm/blackfin.h>



#include "defBF51x_base.h"
@@ -43,57 +42,9 @@ 


/* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/

#define bfin_read_PLL_CTL()			bfin_read16(PLL_CTL)

/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore(flags);

}

#define bfin_read_PLL_DIV()			bfin_read16(PLL_DIV)

#define bfin_write_PLL_DIV(val)			bfin_write16(PLL_DIV, val)

#define bfin_read_VR_CTL()			bfin_read16(VR_CTL)

/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore(flags);

}

#define bfin_read_PLL_STAT()			bfin_read16(PLL_STAT)

#define bfin_write_PLL_STAT(val)		bfin_write16(PLL_STAT, val)

#define bfin_read_PLL_LOCKCNT()			bfin_read16(PLL_LOCKCNT)
@@ -1201,4 +1152,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) 
#define bfin_read_NFC_DATA_RD()			bfin_read16(NFC_DATA_RD)

#define bfin_write_NFC_DATA_RD(val)		bfin_write16(NFC_DATA_RD, val)



/* These need to be last due to the cdef/linux inter-dependencies */

#include <asm/system.h>



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore(flags);

}



#endif /* _CDEF_BF52X_H */

arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h

+53 −49
Original line number Diff line number Diff line
@@ -31,7 +31,6 @@ 
#ifndef _CDEF_BF52X_H

#define _CDEF_BF52X_H



#include <asm/system.h>

#include <asm/blackfin.h>



#include "defBF52x_base.h"
@@ -43,57 +42,9 @@ 


/* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/

#define bfin_read_PLL_CTL()			bfin_read16(PLL_CTL)

/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore(flags);

}

#define bfin_read_PLL_DIV()			bfin_read16(PLL_DIV)

#define bfin_write_PLL_DIV(val)			bfin_write16(PLL_DIV, val)

#define bfin_read_VR_CTL()			bfin_read16(VR_CTL)

/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore(flags);

}

#define bfin_read_PLL_STAT()			bfin_read16(PLL_STAT)

#define bfin_write_PLL_STAT(val)		bfin_write16(PLL_STAT, val)

#define bfin_read_PLL_LOCKCNT()			bfin_read16(PLL_LOCKCNT)
@@ -1201,4 +1152,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) 
#define bfin_read_NFC_DATA_RD()			bfin_read16(NFC_DATA_RD)

#define bfin_write_NFC_DATA_RD(val)		bfin_write16(NFC_DATA_RD, val)



/* These need to be last due to the cdef/linux inter-dependencies */

#include <asm/system.h>



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore(flags);

}



#endif /* _CDEF_BF52X_H */

arch/blackfin/mach-bf533/include/mach/cdefBF532.h

+47 −44
Original line number Diff line number Diff line
@@ -39,31 +39,8 @@ 
/*include core specific register pointer definitions*/

#include <asm/cdef_LPBlackfin.h>



#include <asm/system.h>



/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */

#define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)

/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	local_irq_restore(flags);

}

#define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)

#define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)

#define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
@@ -72,27 +49,6 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val) 
#define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)

#define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)

#define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)

/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	local_irq_restore(flags);

}



/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */

#define bfin_read_SWRST()                    bfin_read16(SWRST)
@@ -764,4 +720,51 @@ BFIN_READ_FIO_FLAG(T) 
#define bfin_read_PPI_FRAME()                bfin_read16(PPI_FRAME)

#define bfin_write_PPI_FRAME(val)            bfin_write16(PPI_FRAME,val)



/* These need to be last due to the cdef/linux inter-dependencies */

#include <asm/system.h>



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	local_irq_restore(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	local_irq_restore(flags);

}



#endif				/* _CDEF_BF532_H */

arch/blackfin/mach-bf537/include/mach/cdefBF534.h

+47 −44
Original line number Diff line number Diff line
@@ -40,55 +40,11 @@ 
/* Include core specific register pointer definitions 								*/

#include <asm/cdef_LPBlackfin.h>



#include <asm/system.h>



/* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/

#define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)

/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	local_irq_restore(flags);

}

#define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)

#define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)

#define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)

/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	local_irq_restore(flags);

}

#define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)

#define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)

#define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
@@ -1816,4 +1772,51 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) 
#define bfin_read_HMDMA1_BCOUNT()            bfin_read16(HMDMA1_BCOUNT)

#define bfin_write_HMDMA1_BCOUNT(val)        bfin_write16(HMDMA1_BCOUNT,val)



/* These need to be last due to the cdef/linux inter-dependencies */

#include <asm/system.h>



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	local_irq_restore(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr = bfin_read32(SIC_IWR);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR, IWR_ENABLE(0));



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR, iwr);

	local_irq_restore(flags);

}



#endif				/* _CDEF_BF534_H */

arch/blackfin/mach-bf538/include/mach/cdefBF538.h

+53 −50
Original line number Diff line number Diff line
@@ -39,62 +39,12 @@ 
/*include core specific register pointer definitions*/

#include <asm/cdef_LPBlackfin.h>



#include <asm/system.h>



#define bfin_writePTR(addr, val) bfin_write32(addr, val)



#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)

/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore(flags);

}

#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)

#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)

#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)

/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore(flags);

}

#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)

#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)

#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
@@ -2102,4 +2052,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) 
#define bfin_read_CAN_MB31_ID1()       bfin_read16(CAN_MB31_ID1)

#define bfin_write_CAN_MB31_ID1(val)   bfin_write16(CAN_MB31_ID1, val)



/* These need to be last due to the cdef/linux inter-dependencies */

#include <asm/system.h>



/* Writing to PLL_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_PLL_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_PLL_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(PLL_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore(flags);

}



/* Writing to VR_CTL initiates a PLL relock sequence. */

static __inline__ void bfin_write_VR_CTL(unsigned int val)

{

	unsigned long flags, iwr0, iwr1;



	if (val == bfin_read_VR_CTL())

		return;



	local_irq_save(flags);

	/* Enable the PLL Wakeup bit in SIC IWR */

	iwr0 = bfin_read32(SIC_IWR0);

	iwr1 = bfin_read32(SIC_IWR1);

	/* Only allow PPL Wakeup) */

	bfin_write32(SIC_IWR0, IWR_ENABLE(0));

	bfin_write32(SIC_IWR1, 0);



	bfin_write16(VR_CTL, val);

	SSYNC();

	asm("IDLE;");



	bfin_write32(SIC_IWR0, iwr0);

	bfin_write32(SIC_IWR1, iwr1);

	local_irq_restore(flags);

}



#endif