Commit 55241865 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Dinh Nguyen
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clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test) 



ARCH_SOCFPGA is being renamed to ARCH_INTEL_SOCFPGA so adjust the
32-bit ARM drivers to rely on new symbol.

There is little point to share clock controller drivers between 32-bit
and 64-bit platforms because there will not be a generic image for both
of them.  Therefore add a new Kconfig entry for building 32-bit clock
driverss, similar to one for 64-bit.  This allows enabling compile
testing.

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent cdb1e8b4

drivers/clk/socfpga/Kconfig

+5 −1
Original line number Diff line number Diff line
@@ -4,10 +4,14 @@ config CLK_INTEL_SOCFPGA 
	default ARCH_INTEL_SOCFPGA

	help

	  Support for the clock controllers present on Intel SoCFPGA and eASIC

	  devices like Stratix 10, Agilex and N5X eASIC.

	  devices like Aria, Cyclone, Stratix 10, Agilex and N5X eASIC.



if CLK_INTEL_SOCFPGA



config CLK_INTEL_SOCFPGA32

	bool "Intel Aria / Cyclone clock controller support" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)

	default ARM && ARCH_INTEL_SOCFPGA



config CLK_INTEL_SOCFPGA64

	bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA)

	default ARM64 && ARCH_INTEL_SOCFPGA

drivers/clk/socfpga/Makefile

+2 −2
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o

obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o

obj-$(CONFIG_CLK_INTEL_SOCFPGA32) += clk.o clk-gate.o clk-pll.o clk-periph.o \

				     clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o

obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-s10.o \

				     clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \

				     clk-agilex.o