Commit 567d37b9 authored by Adam Ford's avatar Adam Ford Committed by Geert Uytterhoeven
Browse files

arm64: boot: dts: r8a774[a/b/e]1-beacon: Consolidate sound clocks 



Each kit-level file represents a SOM + baseboard for a specific
SoC type and uses specific clocks unique to each SoC.  With the
exception of one clock, the rest of the clock info was duplicated.

There is a generic clock called CPG_AUDIO_CLK_I defined in each of
the SoC DTSI files which points to this unique clock. By using that,
the clock information for the rcar_sound can be consolidated into
the baseboard file and have it reference this generic clock thus
removing the duplication from the three variants.

Signed-off-by: default avatarAdam Ford <aford173@gmail.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230104141245.8407-4-aford173@gmail.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent c68b12a9

arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -638,6 +638,25 @@ &rcar_sound { 
	#clock-cells = <1>;

	clock-frequency = <11289600>;



	/* Reference versaclock instead of audio_clk_a */

	clocks = <&cpg CPG_MOD 1005>,

		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,

		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,

		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,

		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,

		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,

		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,

		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,

		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,

		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,

		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,

		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,

		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,

		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,

		 <&versaclock6_bb 4>, <&audio_clk_b>,

		 <&audio_clk_c>,

		 <&cpg CPG_CORE CPG_AUDIO_CLK_I>;



	status = "okay";



	ports {

arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts

+0 −21
Original line number Diff line number Diff line
@@ -58,24 +58,3 @@ &du { 
	clock-names = "du.0", "du.1", "du.2",

		      "dclkin.0", "dclkin.1", "dclkin.2";

};
 


/* Reference versaclock instead of audio_clk_a */

&rcar_sound {

	clocks = <&cpg CPG_MOD 1005>,

		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,

		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,

		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,

		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,

		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,

		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,

		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,

		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,

		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,

		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,

		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,

		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,

		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,

		 <&versaclock6_bb 4>, <&audio_clk_b>,

		 <&audio_clk_c>,

		 <&cpg CPG_CORE R8A774A1_CLK_S0D4>;

};

arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts

+0 −21
Original line number Diff line number Diff line
@@ -46,24 +46,3 @@ &du { 
	clock-names = "du.0", "du.1", "du.3",

		"dclkin.0", "dclkin.1", "dclkin.3";

};
 


/* Reference versaclock instead of audio_clk_a */

&rcar_sound {

	clocks = <&cpg CPG_MOD 1005>,

		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,

		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,

		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,

		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,

		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,

		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,

		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,

		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,

		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,

		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,

		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,

		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,

		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,

		 <&versaclock6_bb 4>, <&audio_clk_b>,

		 <&audio_clk_c>,

		 <&cpg CPG_CORE R8A774B1_CLK_S0D4>;

};

arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts

+0 −21
Original line number Diff line number Diff line
@@ -51,24 +51,3 @@ &du { 
	clock-names = "du.0", "du.1", "du.3",

		"dclkin.0", "dclkin.1", "dclkin.3";

};
 


/* Reference versaclock instead of audio_clk_a */

&rcar_sound {

	clocks = <&cpg CPG_MOD 1005>,

		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,

		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,

		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,

		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,

		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,

		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,

		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,

		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,

		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,

		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,

		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,

		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,

		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,

		 <&versaclock6_bb 4>, <&audio_clk_b>,

		 <&audio_clk_c>,

		 <&cpg CPG_CORE R8A774E1_CLK_S0D4>;

};