Unverified Commit 56a38404 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Mark Brown
Browse files

ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names properties



From R01UH0914EJ0120 Rev.1.20 HW manual, for full duplex channels
(SSI0/1/3) dma_rt interrupt has now being marked as reserved and similarly
for half duplex channel (SSI2) dma_rx and dma_tx interrupts have now being
marked as reserved (this applies to RZ/G2L and alike SoC's). This patch
updates the binding doc to match the same.

While at it also updated the example node.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230217185225.43310-2-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent fe15c26e
Loading
Loading
Loading
Loading
+12 −9
Original line number Diff line number Diff line
@@ -25,13 +25,17 @@ properties:
    maxItems: 1

  interrupts:
    maxItems: 4
    minItems: 2
    maxItems: 3

  interrupt-names:
    items:
    oneOf:
      - items:
          - const: int_req
          - const: dma_rx
          - const: dma_tx
      - items:
          - const: int_req
          - const: dma_rt

  clocks:
@@ -106,9 +110,8 @@ examples:
            reg = <0x10049c00 0x400>;
            interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
            interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
                         <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
            interrupt-names = "int_req", "dma_rx", "dma_tx";
            clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
                     <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
                     <&audio_clk1>,