Commit 57000675 authored by Sricharan Ramabadhran's avatar Sricharan Ramabadhran Committed by Bjorn Andersson
Browse files

arm64: dts: Add ipq5018 SoC and rdp432-c2 board support 



Add initial device tree support for the Qualcomm IPQ5018 SoC and
rdp432-c2 board.

Few things like 'reboot' does not work because, couple of more 'SCM'
APIS are needed to clear some TrustZone settings. Those will be
posted separately.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: default avatarVaradarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: default avatarVaradarajan Narayanan <quic_varada@quicinc.com>
Co-developed-by: default avatarGokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: default avatarGokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: default avatarSricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/1690533192-22220-6-git-send-email-quic_srichara@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent f8100504

arch/arm64/boot/dts/qcom/Makefile

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@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb 
dtb-$(CONFIG_ARCH_QCOM)	+= apq8094-sony-xperia-kitakami-karin_windy.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-db820c.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-ifc6640.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= ipq5018-rdp432-c2.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= ipq5332-rdp441.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= ipq5332-rdp442.dtb

dtb-$(CONFIG_ARCH_QCOM)	+= ipq5332-rdp468.dtb

arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts

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+72 −0
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause

/*

 * IPQ5018 MP03.1-C2 board device tree source

 *

 * Copyright (c) 2023 The Linux Foundation. All rights reserved.

 */



/dts-v1/;



#include "ipq5018.dtsi"



/ {

	model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2";

	compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018";



	aliases {

		serial0 = &blsp1_uart1;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};

};



&blsp1_uart1 {

	pinctrl-0 = <&uart1_pins>;

	pinctrl-names = "default";

	status = "okay";

};



&sdhc_1 {

	pinctrl-0 = <&sdc_default_state>;

	pinctrl-names = "default";

	mmc-ddr-1_8v;

	mmc-hs200-1_8v;

	max-frequency = <192000000>;

	bus-width = <4>;

	status = "okay";

};



&sleep_clk {

	clock-frequency = <32000>;

};



&tlmm {

	sdc_default_state: sdc-default-state {

		clk-pins {

			pins = "gpio9";

			function = "sdc1_clk";

			drive-strength = <8>;

			bias-disable;

		};



		cmd-pins {

			pins = "gpio8";

			function = "sdc1_cmd";

			drive-strength = <8>;

			bias-pull-up;

		};



		data-pins {

			pins = "gpio4", "gpio5", "gpio6", "gpio7";

			function = "sdc1_data";

			drive-strength = <8>;

			bias-disable;

		};

	};

};



&xo_board_clk {

	clock-frequency = <24000000>;

};

arch/arm64/boot/dts/qcom/ipq5018.dtsi

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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause

/*

 * IPQ5018 SoC device tree source

 *

 * Copyright (c) 2023 The Linux Foundation. All rights reserved.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-ipq5018.h>

#include <dt-bindings/reset/qcom,gcc-ipq5018.h>



/ {

	interrupt-parent = <&intc>;

	#address-cells = <2>;

	#size-cells = <2>;



	clocks {

		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

		};



		xo_board_clk: xo-board-clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

		};

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

		};



		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x1>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

		};



		L2_0: l2-cache {

			compatible = "cache";

			cache-level = <2>;

			cache-size = <0x80000>;

			cache-unified;

		};

	};



	firmware {

		scm {

			compatible = "qcom,scm-ipq5018", "qcom,scm";

		};

	};



	memory@40000000 {

		device_type = "memory";

		/* We expect the bootloader to fill in the size */

		reg = <0x0 0x40000000 0x0 0x0>;

	};



	pmu {

		compatible = "arm,cortex-a53-pmu";

		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		tz_region: tz@4ac00000 {

			reg = <0x0 0x4ac00000 0x0 0x200000>;

			no-map;

		};

	};



	soc: soc@0 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0 0xffffffff>;



		tlmm: pinctrl@1000000 {

			compatible = "qcom,ipq5018-tlmm";

			reg = <0x01000000 0x300000>;

			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&tlmm 0 0 47>;

			interrupt-controller;

			#interrupt-cells = <2>;



			uart1_pins: uart1-state {

				pins = "gpio31", "gpio32", "gpio33", "gpio34";

				function = "blsp1_uart1";

				drive-strength = <8>;

				bias-pull-down;

			};

		};



		gcc: clock-controller@1800000 {

			compatible = "qcom,gcc-ipq5018";

			reg = <0x01800000 0x80000>;

			clocks = <&xo_board_clk>,

				 <&sleep_clk>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <0>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		sdhc_1: mmc@7804000 {

			compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";

			reg = <0x7804000 0x1000>;

			reg-names = "hc";



			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";



			clocks = <&gcc GCC_SDCC1_AHB_CLK>,

				 <&gcc GCC_SDCC1_APPS_CLK>,

				 <&xo_board_clk>;

			clock-names = "iface", "core", "xo";

			non-removable;

			status = "disabled";

		};



		blsp1_uart1: serial@78af000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x078af000 0x200>;

			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			status = "disabled";

		};



		intc: interrupt-controller@b000000 {

			compatible = "qcom,msm-qgic2";

			reg = <0x0b000000 0x1000>,  /* GICD */

			      <0x0b002000 0x2000>,  /* GICC */

			      <0x0b001000 0x1000>,  /* GICH */

			      <0x0b004000 0x2000>;  /* GICV */

			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

			interrupt-controller;

			#interrupt-cells = <3>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0 0x0b00a000 0x1ffa>;



			v2m0: v2m@0 {

				compatible = "arm,gic-v2m-frame";

				reg = <0x00000000 0xff8>;

				msi-controller;

			};



			v2m1: v2m@1000 {

				compatible = "arm,gic-v2m-frame";

				reg = <0x00001000 0xff8>;

				msi-controller;

			};

		};



		timer@b120000 {

			compatible = "arm,armv7-timer-mem";

			reg = <0x0b120000 0x1000>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			frame@b120000 {

				reg = <0x0b121000 0x1000>,

				      <0x0b122000 0x1000>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

				frame-number = <0>;

			};



			frame@b123000 {

				reg = <0xb123000 0x1000>;

				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

				frame-number = <1>;

				status = "disabled";

			};



			frame@b124000 {

				frame-number = <2>;

				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b124000 0x1000>;

				status = "disabled";

			};



			frame@b125000 {

				reg = <0x0b125000 0x1000>;

				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				frame-number = <3>;

				status = "disabled";

			};



			frame@b126000 {

				reg = <0x0b126000 0x1000>;

				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

				frame-number = <4>;

				status = "disabled";

			};



			frame@b127000 {

				reg = <0x0b127000 0x1000>;

				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

				frame-number = <5>;

				status = "disabled";

			};



			frame@b128000 {

				reg = <0x0b128000 0x1000>;

				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

				frame-number = <6>;

				status = "disabled";

			};

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};

};