Commit 572e9fd6 authored by Loic Poulain's avatar Loic Poulain Committed by Dmitry Baryshkov
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drm/msm/dsi: Add phy configuration for QCM2290 



The QCM2290 SoC a the 14nm (V2.0) single DSI phy. The platform is not
fully compatible with the standard 14nm PHY, so it requires a separate
compatible and config entry.

Signed-off-by: default avatarLoic Poulain <loic.poulain@linaro.org>
[DB: rebased and updated commit msg]
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/504578/
Link: https://lore.kernel.org/r/20220924121900.222711-3-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 2387771f

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

+2 −0
Original line number Diff line number Diff line
@@ -549,6 +549,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { 
#ifdef CONFIG_DRM_MSM_DSI_14NM_PHY

	{ .compatible = "qcom,dsi-phy-14nm",

	  .data = &dsi_phy_14nm_cfgs },

	{ .compatible = "qcom,dsi-phy-14nm-2290",

	  .data = &dsi_phy_14nm_2290_cfgs },

	{ .compatible = "qcom,dsi-phy-14nm-660",

	  .data = &dsi_phy_14nm_660_cfgs },

	{ .compatible = "qcom,dsi-phy-14nm-8953",

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+1 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; 
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;

drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

+17 −0
Original line number Diff line number Diff line
@@ -1081,3 +1081,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { 
	.io_start = { 0x1a94400, 0x1a96400 },

	.num_dsi_phy = 2,

};



const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {

	.has_phy_lane = true,

	.regulator_data = dsi_phy_14nm_17mA_regulators,

	.num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),

	.ops = {

		.enable = dsi_14nm_phy_enable,

		.disable = dsi_14nm_phy_disable,

		.pll_init = dsi_pll_14nm_init,

		.save_pll_state = dsi_14nm_pll_save_state,

		.restore_pll_state = dsi_14nm_pll_restore_state,

	},

	.min_pll_rate = VCO_MIN_RATE,

	.max_pll_rate = VCO_MAX_RATE,

	.io_start = { 0x5e94400 },

	.num_dsi_phy = 1,

};