Commit 57b2efce authored by Marek Vasut's avatar Marek Vasut Committed by Linus Walleij
Browse files

drm/panel/panel-sitronix-st7701: Add Densitron DMT028VGHMCMI-1A TFT 



Add support for Densitron DMT028VGHMCMI-1A TFT matrix into this driver.
This is a DSI-attached 480x640 2.83 inch panel.

Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Cc: Guido Günther <agx@sigxcpu.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220725151703.319939-2-marex@denx.de
parent e6e62748

drivers/gpu/drm/panel/panel-sitronix-st7701.c

+182 −5
Original line number Diff line number Diff line
@@ -42,13 +42,16 @@ 
/*

 * Command2 with BK function selection.

 *

 * BIT[4, 0]: [CN2, BKXSEL]

 * 10 = CMD2BK0, Command2 BK0

 * 11 = CMD2BK1, Command2 BK1

 * 00 = Command2 disable

 * BIT[4].....CN2

 * BIT[1:0]...BKXSEL

 * 1:00 = CMD2BK0, Command2 BK0

 * 1:01 = CMD2BK1, Command2 BK1

 * 1:11 = CMD2BK3, Command2 BK3

 * 0:00 = Command2 disable

 */

#define DSI_CMD2BK1_SEL			0x11

#define DSI_CMD2BK0_SEL			0x10

#define DSI_CMD2BK1_SEL			0x11

#define DSI_CMD2BK3_SEL			0x13

#define DSI_CMD2BKX_SEL_NONE		0x00



/* Command2, BK0 bytes */
@@ -329,6 +332,78 @@ static void ts8550b_gip_sequence(struct st7701 *st7701) 
		   0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF);

}



static void dmt028vghmcmi_1a_gip_sequence(struct st7701 *st7701)

{

	ST7701_DSI(st7701, 0xEE, 0x42);

	ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);



	ST7701_DSI(st7701, 0xE1,

		   0x04, 0xA0, 0x06, 0xA0,

			   0x05, 0xA0, 0x07, 0xA0,

			   0x00, 0x44, 0x44);

	ST7701_DSI(st7701, 0xE2,

		   0x00, 0x00, 0x00, 0x00,

			   0x00, 0x00, 0x00, 0x00,

			   0x00, 0x00, 0x00, 0x00);

	ST7701_DSI(st7701, 0xE3,

		   0x00, 0x00, 0x22, 0x22);

	ST7701_DSI(st7701, 0xE4, 0x44, 0x44);

	ST7701_DSI(st7701, 0xE5,

		   0x0C, 0x90, 0xA0, 0xA0,

			   0x0E, 0x92, 0xA0, 0xA0,

			   0x08, 0x8C, 0xA0, 0xA0,

			   0x0A, 0x8E, 0xA0, 0xA0);

	ST7701_DSI(st7701, 0xE6,

		   0x00, 0x00, 0x22, 0x22);

	ST7701_DSI(st7701, 0xE7, 0x44, 0x44);

	ST7701_DSI(st7701, 0xE8,

		   0x0D, 0x91, 0xA0, 0xA0,

			   0x0F, 0x93, 0xA0, 0xA0,

			   0x09, 0x8D, 0xA0, 0xA0,

			   0x0B, 0x8F, 0xA0, 0xA0);

	ST7701_DSI(st7701, 0xEB,

		   0x00, 0x00, 0xE4, 0xE4,

			   0x44, 0x00, 0x00);

	ST7701_DSI(st7701, 0xED,

		   0xFF, 0xF5, 0x47, 0x6F,

			   0x0B, 0xA1, 0xAB, 0xFF,

			   0xFF, 0xBA, 0x1A, 0xB0,

			   0xF6, 0x74, 0x5F, 0xFF);

	ST7701_DSI(st7701, 0xEF,

		   0x08, 0x08, 0x08, 0x40,

			   0x3F, 0x64);



	ST7701_DSI(st7701, DSI_CMD2BKX_SEL,

		   0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE);



	ST7701_DSI(st7701, DSI_CMD2BKX_SEL,

		   0x77, 0x01, 0x00, 0x00, DSI_CMD2BK3_SEL);

	ST7701_DSI(st7701, 0xE6, 0x7C);

	ST7701_DSI(st7701, 0xE8, 0x00, 0x0E);



	ST7701_DSI(st7701, DSI_CMD2BKX_SEL,

		   0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE);

	ST7701_DSI(st7701, 0x11);

	msleep(120);



	ST7701_DSI(st7701, DSI_CMD2BKX_SEL,

		   0x77, 0x01, 0x00, 0x00, DSI_CMD2BK3_SEL);

	ST7701_DSI(st7701, 0xE8, 0x00, 0x0C);

	msleep(10);

	ST7701_DSI(st7701, 0xE8, 0x00, 0x00);



	ST7701_DSI(st7701, DSI_CMD2BKX_SEL,

		   0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE);

	ST7701_DSI(st7701, 0x11);

	msleep(120);

	ST7701_DSI(st7701, 0xE8, 0x00, 0x00);



	ST7701_DSI(st7701, DSI_CMD2BKX_SEL,

		   0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE);



	ST7701_DSI(st7701, 0x3A, 0x70);

}



static int st7701_prepare(struct drm_panel *panel)

{

	struct st7701 *st7701 = panel_to_st7701(panel);
@@ -532,6 +607,107 @@ static const struct st7701_panel_desc ts8550b_desc = { 
	.gip_sequence = ts8550b_gip_sequence,

};



static const struct drm_display_mode dmt028vghmcmi_1a_mode = {

	.clock		= 22325,



	.hdisplay	= 480,

	.hsync_start	= 480 + 40,

	.hsync_end	= 480 + 40 + 4,

	.htotal		= 480 + 40 + 4 + 20,



	.vdisplay	= 640,

	.vsync_start	= 640 + 2,

	.vsync_end	= 640 + 2 + 40,

	.vtotal		= 640 + 2 + 40 + 16,



	.width_mm	= 56,

	.height_mm	= 78,



	.flags		= DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,



	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,

};



static const struct st7701_panel_desc dmt028vghmcmi_1a_desc = {

	.mode = &dmt028vghmcmi_1a_mode,

	.lanes = 2,

	.format = MIPI_DSI_FMT_RGB888,

	.panel_sleep_delay = 5, /* panel need extra 5ms for sleep out cmd */



	.pv_gamma = {

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),



		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),



		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11),



		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)

	},

	.nv_gamma = {

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe),



		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),



		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),



		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |

		CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)

	},

	.nlinv = 1,

	.vop_uv = 4800000,

	.vcom_uv = 1650000,

	.vgh_mv = 15000,

	.vgl_mv = -10170,

	.avdd_mv = 6600,

	.avcl_mv = -4400,

	.gamma_op_bias = OP_BIAS_MIDDLE,

	.input_op_bias = OP_BIAS_MIN,

	.output_op_bias = OP_BIAS_MIN,

	.t2d_ns = 1600,

	.t3d_ns = 10400,

	.eot_en = true,

	.gip_sequence = dmt028vghmcmi_1a_gip_sequence,

};



static int st7701_dsi_probe(struct mipi_dsi_device *dsi)

{

	const struct st7701_panel_desc *desc;
@@ -598,6 +774,7 @@ static void st7701_dsi_remove(struct mipi_dsi_device *dsi) 
}



static const struct of_device_id st7701_of_match[] = {

	{ .compatible = "densitron,dmt028vghmcmi-1a", .data = &dmt028vghmcmi_1a_desc },

	{ .compatible = "techstar,ts8550b", .data = &ts8550b_desc },

	{ }

};