Commit 580b8bce authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/dt' 

- Convert Amlogic Meson AXG DWC PCIe SoC controller bindings to dt-schema
  (Neil Armstrong)

- Restructure i.MX schema to extract common properties to be shared by Root
  Complex and Endpoint schema (Richard Zhu)

* pci/controller/dt:
  dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema
  dt-bindings: PCI: convert amlogic,meson-pcie.txt to dt-schema
parents 1c03b5bf b10f8238

Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic Meson AXG DWC PCIe SoC controller



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>



description:

  Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.



allOf:

  - $ref: /schemas/pci/pci-bus.yaml#

  - $ref: /schemas/pci/snps,dw-pcie-common.yaml#



# We need a select here so we don't match all nodes with 'snps,dw-pcie'

select:

  properties:

    compatible:

      enum:

        - amlogic,axg-pcie

        - amlogic,g12a-pcie

  required:

    - compatible



properties:

  compatible:

    items:

      - enum:

          - amlogic,axg-pcie

          - amlogic,g12a-pcie

      - const: snps,dw-pcie



  reg:

    items:

      - description: External local bus interface registers

      - description: Meson designed configuration registers

      - description: PCIe configuration space



  reg-names:

    items:

      - const: elbi

      - const: cfg

      - const: config



  interrupts:

    maxItems: 1



  clocks:

    items:

      - description: PCIe GEN 100M PLL clock

      - description: PCIe RC clock gate

      - description: PCIe PHY clock



  clock-names:

    items:

      - const: pclk

      - const: port

      - const: general



  phys:

    maxItems: 1



  phy-names:

    const: pcie



  resets:

    items:

      - description: Port Reset

      - description: Shared APB reset



  reset-names:

    items:

      - const: port

      - const: apb



  num-lanes:

    const: 1



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - clock

  - clock-names

  - "#address-cells"

  - "#size-cells"

  - "#interrupt-cells"

  - interrupt-map

  - interrupt-map-mask

  - ranges

  - bus-range

  - device_type

  - num-lanes

  - phys

  - phy-names

  - resets

  - reset-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pcie: pcie@f9800000 {

        compatible = "amlogic,axg-pcie", "snps,dw-pcie";

        reg = <0xf9800000 0x400000>, <0xff646000 0x2000>, <0xf9f00000 0x100000>;

        reg-names = "elbi", "cfg", "config";

        interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;

        clocks = <&pclk>, <&clk_port>, <&clk_phy>;

        clock-names = "pclk", "port", "general";

        resets = <&reset_pcie_port>, <&reset_pcie_apb>;

        reset-names = "port", "apb";

        phys = <&pcie_phy>;

        phy-names = "pcie";

        #interrupt-cells = <1>;

        interrupt-map-mask = <0 0 0 0>;

        interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;

        bus-range = <0x0 0xff>;

        #address-cells = <3>;

        #size-cells = <2>;

        device_type = "pci";

        num-lanes = <1>;

        ranges = <0x82000000 0 0 0xf9c00000 0 0x00300000>;

    };

...

Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt

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Amlogic Meson AXG DWC PCIE SoC controller



Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.

It shares common functions with the PCIe DesignWare core driver and

inherits common properties defined in

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.



Additional properties are described here:



Required properties:

- compatible:

	should contain :

	- "amlogic,axg-pcie" for AXG SoC Family

	- "amlogic,g12a-pcie" for G12A SoC Family

	to identify the core.

- reg:

	should contain the configuration address space.

- reg-names: Must be

	- "elbi"	External local bus interface registers

	- "cfg"		Meson specific registers

	- "config"	PCIe configuration space

- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.

- clocks: Must contain an entry for each entry in clock-names.

- clock-names: Must include the following entries:

	- "pclk"       PCIe GEN 100M PLL clock

	- "port"       PCIe_x(A or B) RC clock gate

	- "general"    PCIe Phy clock

- resets: phandle to the reset lines.

- reset-names: must contain "port" and "apb"

       - "port"        Port A or B reset

       - "apb"         Share APB reset

- phys: should contain a phandle to the PCIE phy

- phy-names: must contain "pcie"



- device_type:

	should be "pci". As specified in snps,dw-pcie.yaml





Example configuration:



	pcie: pcie@f9800000 {

			compatible = "amlogic,axg-pcie", "snps,dw-pcie";

			reg = <0x0 0xf9800000 0x0 0x400000

					0x0 0xff646000 0x0 0x2000

					0x0 0xf9f00000 0x0 0x100000>;

			reg-names = "elbi", "cfg", "config";

			reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;

			interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;

			bus-range = <0x0 0xff>;

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;



			clocks = <&clkc CLKID_USB

					&clkc CLKID_PCIE_A

					&clkc CLKID_PCIE_CML_EN0>;

			clock-names = "general",

					"pclk",

					"port";

			resets = <&reset RESET_PCIE_A>,

				<&reset RESET_PCIE_APB>;

			reset-names = "port",

					"apb";

			phys = <&pcie_phy>;

			phy-names = "pcie";

	};

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX6 PCIe RC/EP controller



maintainers:

  - Lucas Stach <l.stach@pengutronix.de>

  - Richard Zhu <hongxing.zhu@nxp.com>



description:

  Generic Freescale i.MX PCIe Root Port and Endpoint controller

  properties.



properties:

  clocks:

    minItems: 3

    items:

      - description: PCIe bridge clock.

      - description: PCIe bus clock.

      - description: PCIe PHY clock.

      - description: Additional required clock entry for imx6sx-pcie,

           imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.



  clock-names:

    minItems: 3

    items:

      - const: pcie

      - const: pcie_bus

      - enum: [ pcie_phy, pcie_aux ]

      - enum: [ pcie_inbound_axi, pcie_aux ]



  num-lanes:

    const: 1



  fsl,imx7d-pcie-phy:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: A phandle to an fsl,imx7d-pcie-phy node. Additional

      required properties for imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie,

      and imx8mq-pcie-ep.



  power-domains:

    minItems: 1

    items:

      - description: The phandle pointing to the DISPLAY domain for

          imx6sx-pcie, imx6sx-pcie-ep, to PCIE_PHY power domain for

          imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie and imx8mq-pcie-ep.

      - description: The phandle pointing to the PCIE_PHY power domains

          for imx6sx-pcie and imx6sx-pcie-ep.



  power-domain-names:

    minItems: 1

    items:

      - const: pcie

      - const: pcie_phy



  resets:

    minItems: 2

    maxItems: 3

    description: Phandles to PCIe-related reset lines exposed by SRC

      IP block. Additional required by imx7d-pcie, imx7d-pcie-ep,

      imx8mq-pcie, and imx8mq-pcie-ep.



  reset-names:

    minItems: 2

    maxItems: 3



  fsl,tx-deemph-gen1:

    description: Gen1 De-emphasis value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



  fsl,tx-deemph-gen2-3p5db:

    description: Gen2 (3.5db) De-emphasis value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



  fsl,tx-deemph-gen2-6db:

    description: Gen2 (6db) De-emphasis value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 20



  fsl,tx-swing-full:

    description: Gen2 TX SWING FULL value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 127



  fsl,tx-swing-low:

    description: TX launch amplitude swing_low value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 127



  fsl,max-link-speed:

    description: Specify PCI Gen for link capability (optional required).

      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter

      requirements and thus for gen2 capability a gen2 compliant clock

      generator should be used and configured.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [1, 2, 3, 4]

    default: 1



  phys:

    maxItems: 1



  phy-names:

    const: pcie-phy



  vpcie-supply:

    description: Should specify the regulator in charge of PCIe port power.

      The regulator will be enabled when initializing the PCIe host and

      disabled either as part of the init process or when shutting down

      the host (optional required).



  vph-supply:

    description: Should specify the regulator in charge of VPH one of

      the three PCIe PHY powers. This regulator can be supplied by both

      1.8v and 3.3v voltage supplies (optional required).



required:

  - clocks

  - clock-names

  - num-lanes



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx6sx-pcie

              - fsl,imx6sx-pcie-ep

    then:

      properties:

        clock-names:

          items:

            - {}

            - {}

            - const: pcie_phy

            - const: pcie_inbound_axi

        power-domains:

          minItems: 2

        power-domain-names:

          minItems: 2



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8mq-pcie

              - fsl,imx8mq-pcie-ep

    then:

      properties:

        clock-names:

          items:

            - {}

            - {}

            - const: pcie_phy

            - const: pcie_aux

  - if:

      properties:

        compatible:

          not:

            contains:

              enum:

                - fsl,imx6sx-pcie

                - fsl,imx8mq-pcie

                - fsl,imx6sx-pcie-ep

                - fsl,imx8mq-pcie-ep

    then:

      properties:

        clocks:

          maxItems: 3

        clock-names:

          maxItems: 3



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx6q-pcie

              - fsl,imx6qp-pcie

              - fsl,imx7d-pcie

              - fsl,imx6q-pcie-ep

              - fsl,imx6qp-pcie-ep

              - fsl,imx7d-pcie-ep

    then:

      properties:

        clock-names:

          maxItems: 3

          contains:

            const: pcie_phy



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8mm-pcie

              - fsl,imx8mp-pcie

              - fsl,imx8mm-pcie-ep

              - fsl,imx8mp-pcie-ep

    then:

      properties:

        clock-names:

          maxItems: 3

          contains:

            const: pcie_aux

  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx6q-pcie

              - fsl,imx6qp-pcie

              - fsl,imx6q-pcie-ep

              - fsl,imx6qp-pcie-ep

    then:

      properties:

        power-domains: false

        power-domain-names: false



  - if:

      not:

        properties:

          compatible:

            contains:

              enum:

                - fsl,imx6sx-pcie

                - fsl,imx6q-pcie

                - fsl,imx6qp-pcie

                - fsl,imx6sx-pcie-ep

                - fsl,imx6q-pcie-ep

                - fsl,imx6qp-pcie-ep

    then:

      properties:

        power-domains:

          maxItems: 1

        power-domain-names: false



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx6q-pcie

              - fsl,imx6sx-pcie

              - fsl,imx6qp-pcie

              - fsl,imx7d-pcie

              - fsl,imx8mq-pcie

              - fsl,imx6q-pcie-ep

              - fsl,imx6sx-pcie-ep

              - fsl,imx6qp-pcie-ep

              - fsl,imx7d-pcie-ep

              - fsl,imx8mq-pcie-ep

    then:

      properties:

        resets:

          minItems: 3

        reset-names:

          items:

            - const: pciephy

            - const: apps

            - const: turnoff

    else:

      properties:

        resets:

          maxItems: 2

        reset-names:

          items:

            - const: apps

            - const: turnoff



additionalProperties: true



...

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX6 PCIe Endpoint controller



maintainers:

  - Lucas Stach <l.stach@pengutronix.de>

  - Richard Zhu <hongxing.zhu@nxp.com>



description: |+

  This PCIe controller is based on the Synopsys DesignWare PCIe IP and

  thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.

  The controller instances are dual mode where in they can work either in

  Root Port mode or Endpoint mode but one at a time.



properties:

  compatible:

    enum:

      - fsl,imx8mm-pcie-ep

      - fsl,imx8mq-pcie-ep

      - fsl,imx8mp-pcie-ep



  reg:

    minItems: 2



  reg-names:

    items:

      - const: dbi

      - const: addr_space



  interrupts:

    items:

      - description: builtin eDMA interrupter.



  interrupt-names:

    items:

      - const: dma



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - interrupt-names



allOf:

  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#

  - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/imx8mp-clock.h>

    #include <dt-bindings/power/imx8mp-power.h>

    #include <dt-bindings/reset/imx8mp-reset.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    pcie_ep: pcie-ep@33800000 {

      compatible = "fsl,imx8mp-pcie-ep";

      reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;

      reg-names = "dbi", "addr_space";

      clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,

               <&clk IMX8MP_CLK_HSIO_AXI>,

               <&clk IMX8MP_CLK_PCIE_ROOT>;

      clock-names = "pcie", "pcie_bus", "pcie_aux";

      assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;

      assigned-clock-rates = <10000000>;

      assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;

      num-lanes = <1>;

      interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */

      interrupt-names = "dma";

      fsl,max-link-speed = <3>;

      power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;

      resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,

               <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;

      reset-names = "apps", "turnoff";

      phys = <&pcie_phy>;

      phy-names = "pcie-phy";

      num-ib-windows = <4>;

      num-ob-windows = <4>;

    };

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml

+6 −234
Original line number Diff line number Diff line
@@ -13,6 +13,11 @@ maintainers: 
description: |+

  This PCIe host controller is based on the Synopsys DesignWare PCIe IP

  and thus inherits all the common properties defined in snps,dw-pcie.yaml.

  The controller instances are dual mode where in they can work either in

  Root Port mode or Endpoint mode but one at a time.



  See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree

  bindings.



properties:

  compatible:
@@ -24,9 +29,6 @@ properties: 
      - fsl,imx8mq-pcie

      - fsl,imx8mm-pcie

      - fsl,imx8mp-pcie

      - fsl,imx8mm-pcie-ep

      - fsl,imx8mq-pcie-ep

      - fsl,imx8mp-pcie-ep



  reg:

    items:
@@ -46,96 +48,6 @@ properties: 
    items:

      - const: msi



  clocks:

    minItems: 3

    items:

      - description: PCIe bridge clock.

      - description: PCIe bus clock.

      - description: PCIe PHY clock.

      - description: Additional required clock entry for imx6sx-pcie,

          imx8mq-pcie.



  clock-names:

    minItems: 3

    items:

      - const: pcie

      - const: pcie_bus

      - enum: [ pcie_phy, pcie_aux ]

      - enum: [ pcie_inbound_axi, pcie_aux ]



  num-lanes:

    const: 1



  fsl,imx7d-pcie-phy:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: A phandle to an fsl,imx7d-pcie-phy node. Additional

      required properties for imx7d-pcie and imx8mq-pcie.



  power-domains:

    minItems: 1

    items:

      - description: The phandle pointing to the DISPLAY domain for

          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and

          imx8mq-pcie.

      - description: The phandle pointing to the PCIE_PHY power domains

          for imx6sx-pcie.



  power-domain-names:

    minItems: 1

    items:

      - const: pcie

      - const: pcie_phy



  resets:

    minItems: 2

    maxItems: 3

    description: Phandles to PCIe-related reset lines exposed by SRC

      IP block. Additional required by imx7d-pcie and imx8mq-pcie.



  reset-names:

    minItems: 2

    maxItems: 3



  fsl,tx-deemph-gen1:

    description: Gen1 De-emphasis value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



  fsl,tx-deemph-gen2-3p5db:

    description: Gen2 (3.5db) De-emphasis value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



  fsl,tx-deemph-gen2-6db:

    description: Gen2 (6db) De-emphasis value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 20



  fsl,tx-swing-full:

    description: Gen2 TX SWING FULL value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 127



  fsl,tx-swing-low:

    description: TX launch amplitude swing_low value (optional required).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 127



  fsl,max-link-speed:

    description: Specify PCI Gen for link capability (optional required).

      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter

      requirements and thus for gen2 capability a gen2 compliant clock

      generator should be used and configured.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [1, 2, 3, 4]

    default: 1



  phys:

    maxItems: 1



  phy-names:

    const: pcie-phy



  reset-gpio:

    description: Should specify the GPIO for controlling the PCI bus device

      reset signal. It's not polarity aware and defaults to active-low reset
@@ -147,17 +59,6 @@ properties: 
      L=operation state) (optional required).

    type: boolean



  vpcie-supply:

    description: Should specify the regulator in charge of PCIe port power.

      The regulator will be enabled when initializing the PCIe host and

      disabled either as part of the init process or when shutting down

      the host (optional required).



  vph-supply:

    description: Should specify the regulator in charge of VPH one of

      the three PCIe PHY powers. This regulator can be supplied by both

      1.8v and 3.3v voltage supplies (optional required).



required:

  - compatible

  - reg
@@ -167,144 +68,15 @@ required: 
  - device_type

  - bus-range

  - ranges

  - num-lanes

  - interrupts

  - interrupt-names

  - "#interrupt-cells"

  - interrupt-map-mask

  - interrupt-map

  - clocks

  - clock-names



allOf:

  - $ref: /schemas/pci/snps,dw-pcie.yaml#

  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx6sx-pcie

    then:

      properties:

        clock-names:

          items:

            - {}

            - {}

            - const: pcie_phy

            - const: pcie_inbound_axi

        power-domains:

          minItems: 2

        power-domain-names:

          minItems: 2

  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx8mq-pcie

    then:

      properties:

        clock-names:

          items:

            - {}

            - {}

            - const: pcie_phy

            - const: pcie_aux

  - if:

      properties:

        compatible:

          not:

            contains:

              enum:

                - fsl,imx6sx-pcie

                - fsl,imx8mq-pcie

    then:

      properties:

        clocks:

          maxItems: 3

        clock-names:

          maxItems: 3



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx6q-pcie

              - fsl,imx6qp-pcie

              - fsl,imx7d-pcie

    then:

      properties:

        clock-names:

          maxItems: 3

          contains:

            const: pcie_phy



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8mm-pcie

              - fsl,imx8mp-pcie

    then:

      properties:

        clock-names:

          maxItems: 3

          contains:

            const: pcie_aux

  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx6q-pcie

              - fsl,imx6qp-pcie

    then:

      properties:

        power-domains: false

        power-domain-names: false



  - if:

      not:

        properties:

          compatible:

            contains:

              enum:

                - fsl,imx6sx-pcie

                - fsl,imx6q-pcie

                - fsl,imx6qp-pcie

    then:

      properties:

        power-domains:

          maxItems: 1

        power-domain-names: false



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx6q-pcie

              - fsl,imx6sx-pcie

              - fsl,imx6qp-pcie

              - fsl,imx7d-pcie

              - fsl,imx8mq-pcie

    then:

      properties:

        resets:

          minItems: 3

        reset-names:

          items:

            - const: pciephy

            - const: apps

            - const: turnoff

    else:

      properties:

        resets:

          maxItems: 2

        reset-names:

          items:

            - const: apps

            - const: turnoff

  - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#



unevaluatedProperties: false