Merge tag 'arm-platform-removal-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/sirf.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: CSR SiRFprimaII and SiRFmarco device tree bindings.

maintainers:

  - Binghua Duan <binghua.duan@csr.com>

  - Barry Song <Baohua.Song@csr.com>

properties:

  $nodename:

    const: '/'

  compatible:

    oneOf:

      - items:

          - const: sirf,atlas6-cb

          - const: sirf,atlas6

      - items:

          - const: sirf,atlas7-cb

          - const: sirf,atlas7

      - items:

          - const: sirf,prima2-cb

          - const: sirf,prima2

additionalProperties: true

...

ST-Ericsson U300 Device Tree Bindings

For various board the "board" node may contain specific properties

that pertain to this particular board, such as board-specific GPIOs

or board power regulator supplies.

Required root node property:

compatible="stericsson,u300";

Required node: syscon

This contains the system controller.

- compatible: must be "stericsson,u300-syscon".

- reg: the base address and size of the system controller.

Boards with the U300 SoC include:

S365 "Small Board U365":

Required node: s365

This contains the board-specific information.

- compatible: must be "stericsson,s365".

- vana15-supply: the regulator supplying the 1.5V to drive the

  board.

- syscon: a pointer to the syscon node so we can access the

  syscon registers to set the board as self-powered.

Example:

/ {

	model = "ST-Ericsson U300";

	compatible = "stericsson,u300";

	#address-cells = <1>;

	#size-cells = <1>;

	s365 {

		compatible = "stericsson,s365";

		vana15-supply = <&ab3100_ldo_d_reg>;

		syscon = <&syscon>;

	};

	syscon: syscon@c0011000 {

		compatible = "stericsson,u300-syscon";

		reg = <0xc0011000 0x1000>;

	};

};

ZTE sysctrl Registers

Registers for 'zte,zx296702' SoC:

System management required properties:

      - compatible = "zte,sysctrl"

Low power management required properties:

      - compatible = "zte,zx296702-pcu"

Bus matrix required properties:

      - compatible = "zte,zx-bus-matrix"

Registers for 'zte,zx296718' SoC:

System management required properties:

      - compatible = "zte,zx296718-aon-sysctrl"

      - compatible = "zte,zx296718-sysctrl"

Example:

aon_sysctrl: aon-sysctrl@116000 {

	compatible = "zte,zx296718-aon-sysctrl", "syscon";

	reg = <0x116000 0x1000>;

};

sysctrl: sysctrl@1463000 {

	compatible = "zte,zx296718-sysctrl", "syscon";

	reg = <0x1463000 0x1000>;

};

# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/zte.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ZTE platforms device tree bindings

maintainers:

  - Jun Nie <jun.nie@linaro.org>

properties:

  $nodename:

    const: '/'

  compatible:

    oneOf:

      - items:

          - enum:

              - zte,zx296702-ad1

          - const: zte,zx296702

      - items:

          - enum:

              - zte,zx296718-evb

          - const: zte,zx296718

additionalProperties: true

...

C6X PLL Clock Controllers

-------------------------

This is a first-cut support for the SoC clock controllers. This is still

under development and will probably change as the common device tree

clock support is added to the kernel.

Required properties:

- compatible: "ti,c64x+pll"

    May also have SoC-specific value to support SoC-specific initialization

    in the driver. One of:

        "ti,c6455-pll"

        "ti,c6457-pll"

        "ti,c6472-pll"

        "ti,c6474-pll"

- reg: base address and size of register area

- clock-frequency: input clock frequency in hz

Optional properties:

- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode

- ti,c64x+pll-reset-delay:  CPU cycles to delay after PLL reset

- ti,c64x+pll-lock-delay:   CPU cycles to delay after PLL frequency change

Example:

	clock-controller@29a0000 {

		compatible = "ti,c6472-pll", "ti,c64x+pll";

		reg = <0x029a0000 0x200>;

		clock-frequency = <25000000>;

		ti,c64x+pll-bypass-delay = <200>;

		ti,c64x+pll-reset-delay = <12000>;

		ti,c64x+pll-lock-delay = <80000>;

	};