Commit 588c8a2d authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Update alderlake to v1.20 



Update from v1.19 to v1.20 affecting the performance/goldencove
events. Adds cmask=1 for ARITH.IDIV_ACTIVE, and updates event
descriptions.

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230411234440.3313680-2-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent e0137336

tools/perf/pmu-events/arch/x86/alderlake/other.json

+2 −1
Original line number Diff line number Diff line
@@ -162,10 +162,11 @@ 
        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "XQ.FULL_CYCLES",

        "BriefDescription": "Cycles the uncore cannot take further requests",

        "CounterMask": "1",

        "EventCode": "0x2d",

        "EventName": "XQ.FULL_CYCLES",

        "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).",

        "SampleAfterValue": "1000003",

        "UMask": "0x1",

        "Unit": "cpu_core"

tools/perf/pmu-events/arch/x86/alderlake/pipeline.json

+3 −1
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
    },

    {

        "BriefDescription": "This event counts the cycles the integer divider is busy.",

        "CounterMask": "1",

        "EventCode": "0xb0",

        "EventName": "ARITH.IDIV_ACTIVE",

        "SampleAfterValue": "1000003",
@@ -1079,9 +1080,10 @@ 
        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "MISC2_RETIRED.LFENCE",

        "BriefDescription": "LFENCE instructions retired",

        "EventCode": "0xe0",

        "EventName": "MISC2_RETIRED.LFENCE",

        "PublicDescription": "number of LFENCE retired instructions",

        "SampleAfterValue": "400009",

        "UMask": "0x20",

        "Unit": "cpu_core"

tools/perf/pmu-events/arch/x86/mapfile.csv

+2 −2
Original line number Diff line number Diff line 
Family-model,Version,Filename,EventType

GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core

GenuineIntel-6-BE,v1.19,alderlaken,core

GenuineIntel-6-(97|9A|B7|BA|BF),v1.20,alderlake,core

GenuineIntel-6-BE,v1.20,alderlaken,core

GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core

GenuineIntel-6-(3D|47),v27,broadwell,core

GenuineIntel-6-56,v9,broadwellde,core