Commit 59fd7d32 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events: Update Intel skylakex 

Update to v1.28, the metrics are based on TMA 4.4 full.

Use script at:
https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py



to download and generate the latest events and metrics. Manually copy
the skylakex files into perf and update mapfile.csv.

Tested with 'perf test':
 10: PMU events                                                      :
 10.1: PMU event table sanity                                        : Ok
 10.2: PMU event map aliases                                         : Ok
 10.3: Parsing of PMU event table metrics                            : Ok
 10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
 90: perf all metricgroups test                                      : Ok
 91: perf all metrics test                                           : Skip
 93: perf all PMU test                                               : Ok

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: http://lore.kernel.org/lkml/20220727220832.2865794-26-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 35d65277

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −1
Original line number Diff line number Diff line
@@ -23,10 +23,10 @@ GenuineIntel-6-2A,v17,sandybridge,core 
GenuineIntel-6-8F,v1.04,sapphirerapids,core

GenuineIntel-6-(37|4C|4D),v14,silvermont,core

GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core

GenuineIntel-6-55-[01234],v1.28,skylakex,core

GenuineIntel-6-2C,v2,westmereep-dp,core

GenuineIntel-6-25,v2,westmereep-sp,core

GenuineIntel-6-2F,v2,westmereex,core

GenuineIntel-6-55-[01234],v1,skylakex,core

GenuineIntel-6-8[CD],v1,tigerlake,core

GenuineIntel-6-86,v1,snowridgex,core

AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core

tools/perf/pmu-events/arch/x86/skylakex/other.json

+65 −1
Original line number Diff line number Diff line
@@ -39,6 +39,69 @@ 
        "SampleAfterValue": "200003",

        "UMask": "0x40"

    },

    {

        "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xEF",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",

        "SampleAfterValue": "2000003",

        "UMask": "0x20"

    },

    {

        "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xEF",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM",

        "SampleAfterValue": "2000003",

        "UMask": "0x10"

    },

    {

        "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xEF",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",

        "SampleAfterValue": "2000003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xEF",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI",

        "SampleAfterValue": "2000003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xEF",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",

        "SampleAfterValue": "2000003",

        "UMask": "0x40"

    },

    {

        "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xEF",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM",

        "SampleAfterValue": "2000003",

        "UMask": "0x8"

    },

    {

        "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xEF",

        "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",

        "SampleAfterValue": "2000003",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Number of hardware interrupts received by the processor.",

        "Counter": "0,1,2,3",
@@ -70,6 +133,7 @@ 
        "UMask": "0x2"

    },

    {

        "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x09",

tools/perf/pmu-events/arch/x86/skylakex/pipeline.json

+11 −0
Original line number Diff line number Diff line
@@ -165,6 +165,17 @@ 
        "SampleAfterValue": "400009",

        "UMask": "0x20"

    },

    {

        "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xC5",

        "EventName": "BR_MISP_RETIRED.RET",

        "PEBS": "1",

        "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",

        "SampleAfterValue": "100007",

        "UMask": "0x8"

    },

    {

        "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",

        "Counter": "0,1,2,3",

tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json

+602 −65

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json

+9 −0
Original line number Diff line number Diff line
@@ -84,6 +84,15 @@ 
        "UMask": "0x4",

        "Unit": "iMC"

    },

    {

        "BriefDescription": "Pre-charge for writes",

        "Counter": "0,1,2,3",

        "EventCode": "0x2",

        "EventName": "UNC_M_PRE_COUNT.WR",

        "PerPkg": "1",

        "UMask": "0x8",

        "Unit": "iMC"

    },

    {

        "BriefDescription": "DRAM Page Activate commands sent due to a write request",

        "Counter": "0,1,2,3",