Unverified Commit 5a75c295 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.19-next-dts64' of... 

Merge tag 'v5.19-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

Some fixes to follow DT spec.

MT6795:
- Big update of supported devices: cpu-map, L2 cache, PMU, watchdog,
  MediaTek timer, Arm CCI, pincontroller

MT7622:
- Change WPS button to active low

MT8173:
- Add infracfg property to the IOMMU node (also for mt2712e)
- Add optional AXI clock to NOR Flash node

MT8183:
- add Medaitek CCI support
- add support for Smart Voltag Scaling (SVS)
- add GCE support to mutex
- Add panel default rotation to some chromebooks
- Add power supply to power domain so that SRAM for the GPU has power

MT8186:
- compatible added, DTS not yet ready.

MT8192:
- Add support for Acer Chromebook 514

MT8195:
- Add efuse node
- Enable USB wakeup support
- Add support for Acer Chromebook Spin 513

* tag 'v5.19-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (66 commits)
  arm64: dts: mt8183: Add panel rotation
  arm64: dts: mt7622: fix BPI-R64 WPS button
  arm64: dts: mt8173: Fix nor_flash node
  arm64: dts: mediatek: cherry: Add I2C-HID touchscreen on I2C4
  arm64: dts: mediatek: cherry: Enable support for the SPI NOR flash
  arm64: dts: mediatek: cherry: Enable MT6360 sub-pmic on I2C7
  arm64: dts: mediatek: cherry: Enable T-PHYs and USB XHCI controllers
  arm64: dts: mediatek: cherry: Enable I2C and SPI controllers
  arm64: dts: mediatek: cherry: Document gpios and add default pin config
  arm64: dts: mediatek: cherry: Add support for internal eMMC storage
  arm64: dts: mediatek: cherry: Assign interrupt line to MT6359 PMIC
  arm64: dts: mediatek: cherry: Add platform regulators layout and config
  arm64: dts: mediatek: Introduce MT8195 Cherry platform's Tomato
  dt-bindings: arm: mediatek: Add MT8195 Cherry Tomato Chromebooks
  arm64: dts: mediatek: asurada: Add SPI NOR flash memory
  arm64: dts: mediatek: asurada: Enable SCP
  arm64: dts: mediatek: asurada: Enable MMC
  arm64: dts: mediatek: asurada: Add SPMI regulators
  arm64: dts: mediatek: asurada: Add MT6359 PMIC
  arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
  ...

Link: https://lore.kernel.org/r/b0d5b584-2693-73b3-79f6-3e2292f006ea@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 1a110d77 9c610515

Documentation/devicetree/bindings/arm/mediatek.yaml

+30 −0
Original line number Diff line number Diff line
@@ -131,6 +131,36 @@ properties: 
          - enum:

              - mediatek,mt8183-evb

          - const: mediatek,mt8183

      - description: Google Hayato

        items:

          - const: google,hayato-rev1

          - const: google,hayato

          - const: mediatek,mt8192

      - description: Google Spherion (Acer Chromebook 514)

        items:

          - const: google,spherion-rev3

          - const: google,spherion-rev2

          - const: google,spherion-rev1

          - const: google,spherion-rev0

          - const: google,spherion

          - const: mediatek,mt8192

      - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H)

        items:

          - enum:

              - google,tomato-rev2

              - google,tomato-rev1

          - const: google,tomato

          - const: mediatek,mt8195

      - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H)

        items:

          - const: google,tomato-rev4

          - const: google,tomato-rev3

          - const: google,tomato

          - const: mediatek,mt8195

      - items:

          - enum:

              - mediatek,mt8186-evb

          - const: mediatek,mt8186

      - items:

          - enum:

              - mediatek,mt8192-evb

Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ properties: 
              - mediatek,mt8135-pericfg

              - mediatek,mt8173-pericfg

              - mediatek,mt8183-pericfg

              - mediatek,mt8186-pericfg

              - mediatek,mt8195-pericfg

              - mediatek,mt8516-pericfg

          - const: syscon

arch/arm64/boot/dts/mediatek/Makefile

+5 −0
Original line number Diff line number Diff line
@@ -37,7 +37,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb 
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb

arch/arm64/boot/dts/mediatek/mt2712e.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -329,6 +329,7 @@ iommu0: iommu@10205000 { 
		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&infracfg CLK_INFRA_M4U>;

		clock-names = "bclk";

		mediatek,infracfg = <&infracfg>;

		mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,

				 <&larb3>, <&larb6>;

		#iommu-cells = <1>;
@@ -346,6 +347,7 @@ iommu1: iommu@1020a000 { 
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&infracfg CLK_INFRA_M4U>;

		clock-names = "bclk";

		mediatek,infracfg = <&infracfg>;

		mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;

		#iommu-cells = <1>;

	};

arch/arm64/boot/dts/mediatek/mt6795.dtsi

+205 −55
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 


#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/pinctrl/mt6795-pinfunc.h>



/ {

	compatible = "mediatek,mt6795";
@@ -34,6 +35,8 @@ cpu0: cpu@0 { 
			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x000>;

			cci-control-port = <&cci_control2>;

			next-level-cache = <&l2_0>;

		};



		cpu1: cpu@1 {
@@ -41,6 +44,8 @@ cpu1: cpu@1 { 
			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x001>;

			cci-control-port = <&cci_control2>;

			next-level-cache = <&l2_0>;

		};



		cpu2: cpu@2 {
@@ -48,6 +53,8 @@ cpu2: cpu@2 { 
			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x002>;

			cci-control-port = <&cci_control2>;

			next-level-cache = <&l2_0>;

		};



		cpu3: cpu@3 {
@@ -55,6 +62,8 @@ cpu3: cpu@3 { 
			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x003>;

			cci-control-port = <&cci_control2>;

			next-level-cache = <&l2_0>;

		};



		cpu4: cpu@100 {
@@ -62,6 +71,8 @@ cpu4: cpu@100 { 
			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x100>;

			cci-control-port = <&cci_control1>;

			next-level-cache = <&l2_1>;

		};



		cpu5: cpu@101 {
@@ -69,6 +80,8 @@ cpu5: cpu@101 { 
			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x101>;

			cci-control-port = <&cci_control1>;

			next-level-cache = <&l2_1>;

		};



		cpu6: cpu@102 {
@@ -76,6 +89,8 @@ cpu6: cpu@102 { 
			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x102>;

			cci-control-port = <&cci_control1>;

			next-level-cache = <&l2_1>;

		};



		cpu7: cpu@103 {
@@ -83,27 +98,88 @@ cpu7: cpu@103 { 
			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x103>;

			cci-control-port = <&cci_control1>;

			next-level-cache = <&l2_1>;

		};



		cpu-map {

			cluster0 {

				core0 {

					cpu = <&cpu0>;

				};



	system_clk: dummy13m {

				core1 {

					cpu = <&cpu1>;

				};



				core2 {

					cpu = <&cpu2>;

				};



				core3 {

					cpu = <&cpu3>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&cpu4>;

				};



				core1 {

					cpu = <&cpu5>;

				};



				core2 {

					cpu = <&cpu6>;

				};



				core3 {

					cpu = <&cpu7>;

				};

			};

		};



		l2_0: l2-cache0 {

			compatible = "cache";

			cache-level = <2>;

		};



		l2_1: l2-cache1 {

			compatible = "cache";

			cache-level = <2>;

		};

	};



	clk26m: oscillator-26m {

		compatible = "fixed-clock";

		clock-frequency = <13000000>;

		#clock-cells = <0>;

		clock-frequency = <26000000>;

		clock-output-names = "clk26m";

	};



	rtc_clk: dummy32k {

	clk32k: oscillator-32k {

		compatible = "fixed-clock";

		clock-frequency = <32000>;

		#clock-cells = <0>;

		clock-frequency = <32000>;

		clock-output-names = "clk32k";

	};



	uart_clk: dummy26m {

	system_clk: dummy13m {

		compatible = "fixed-clock";

		clock-frequency = <26000000>;

		clock-frequency = <13000000>;

		#clock-cells = <0>;

	};



	pmu {

		compatible = "arm,cortex-a53-pmu";

		interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI  9 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;

		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupt-parent = <&gic>;
@@ -117,6 +193,41 @@ timer { 
			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;

	};



	soc {

		#address-cells = <2>;

		#size-cells = <2>;

		compatible = "simple-bus";

		ranges;



		pio: pinctrl@10005000 {

			compatible = "mediatek,mt6795-pinctrl";

			reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;

			reg-names = "base", "eint";

			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;

			gpio-controller;

			#gpio-cells = <2>;

			gpio-ranges = <&pio 0 0 196>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		watchdog: watchdog@10007000 {

			compatible = "mediatek,mt6795-wdt";

			reg = <0 0x10007000 0 0x100>;

			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;

			#reset-cells = <1>;

			timeout-sec = <20>;

		};



		timer: timer@10008000 {

			compatible = "mediatek,mt6795-timer",

				     "mediatek,mt6577-timer";

			reg = <0 0x10008000 0 0x1000>;

			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;

			clocks = <&system_clk>, <&clk32k>;

		};



		sysirq: intpol-controller@10200620 {

			compatible = "mediatek,mt6795-sysirq",

				     "mediatek,mt6577-sysirq";
@@ -135,6 +246,44 @@ gic: interrupt-controller@10221000 { 
			      <0 0x10222000 0 0x2000>,

			      <0 0x10224000 0 0x2000>,

			      <0 0x10226000 0 0x2000>;

			interrupts = <GIC_PPI 9

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

		};



		cci: cci@10390000 {

			compatible = "arm,cci-400";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <0 0x10390000 0 0x1000>;

			ranges = <0 0 0x10390000 0x10000>;



			cci_control0: slave-if@1000 {

				compatible = "arm,cci-400-ctrl-if";

				interface-type = "ace-lite";

				reg = <0x1000 0x1000>;

			};



			cci_control1: slave-if@4000 {

				compatible = "arm,cci-400-ctrl-if";

				interface-type = "ace";

				reg = <0x4000 0x1000>;

			};



			cci_control2: slave-if@5000 {

				compatible = "arm,cci-400-ctrl-if";

				interface-type = "ace";

				reg = <0x5000 0x1000>;

			};



			pmu@9000 {

				compatible = "arm,cci-400-pmu,r1";

				reg = <0x9000 0x5000>;

				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

			};

		};



		uart0: serial@11002000 {
@@ -142,7 +291,7 @@ uart0: serial@11002000 { 
				     "mediatek,mt6577-uart";

			reg = <0 0x11002000 0 0x400>;

			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&uart_clk>;

			clocks = <&clk26m>;

			status = "disabled";

		};
@@ -151,7 +300,7 @@ uart1: serial@11003000 { 
				     "mediatek,mt6577-uart";

			reg = <0 0x11003000 0 0x400>;

			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&uart_clk>;

			clocks = <&clk26m>;

			status = "disabled";

		};
@@ -160,7 +309,7 @@ uart2: serial@11004000 { 
				     "mediatek,mt6577-uart";

			reg = <0 0x11004000 0 0x400>;

			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&uart_clk>;

			clocks = <&clk26m>;

			status = "disabled";

		};
@@ -169,7 +318,8 @@ uart3: serial@11005000 { 
				     "mediatek,mt6577-uart";

			reg = <0 0x11005000 0 0x400>;

			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&uart_clk>;

			clocks = <&clk26m>;

			status = "disabled";

		};

	};

};