Commit 5ab5d404 authored by Alexandre Courbot's avatar Alexandre Courbot Committed by Peter De Schrijver
Browse files

clk: tegra: add FUSE clock device 



This clock is needed to ensure the FUSE registers can be accessed
without freezing the system.

Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
parent c04bf559

drivers/clk/tegra/clk-tegra114.c

+1 −0
Original line number Diff line number Diff line
@@ -918,6 +918,7 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },

	{ .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },

	{ .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },

	{ .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },

	{ .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },

	{ .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },

};

drivers/clk/tegra/clk-tegra124.c

+1 −0
Original line number Diff line number Diff line
@@ -1009,6 +1009,7 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },

	{ .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },

	{ .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },

	{ .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },

	{ .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },

	{ .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },

};

drivers/clk/tegra/clk-tegra20.c

+1 −0
Original line number Diff line number Diff line
@@ -446,6 +446,7 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },

	{ .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },

	{ .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },

	{ .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE },

	{ .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },

	{ .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },

	{ .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },

drivers/clk/tegra/clk-tegra30.c

+1 −1
Original line number Diff line number Diff line
@@ -650,7 +650,7 @@ static struct tegra_devclk devclks[] __initdata = { 
	{ .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },

	{ .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },

	{ .con_id = "pciex", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIEX },

	{ .con_id = "fuse", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE },

	{ .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },

	{ .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },

	{ .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },

	{ .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },