Commit 5bb9d267 authored by Peter De Schrijver's avatar Peter De Schrijver
Browse files

clk: tegra: Add TEGRA_PERIPH_NO_DIV flag 



This flag indicates the peripheral clock does not have a divider. It will
simplify the initialization tables and avoids some very similar code.

Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
parent 343a607c

drivers/clk/tegra/clk-periph.c

+8 −3
Original line number Diff line number Diff line
@@ -173,12 +173,16 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = { 
static struct clk *_tegra_clk_register_periph(const char *name,

			const char **parent_names, int num_parents,

			struct tegra_clk_periph *periph,

			void __iomem *clk_base, u32 offset, bool div,

			void __iomem *clk_base, u32 offset,

			unsigned long flags)

{

	struct clk *clk;

	struct clk_init_data init;

	struct tegra_clk_periph_regs *bank;

	bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV);



	flags |= periph->gate.flags & TEGRA_PERIPH_NO_DIV ?

			CLK_SET_RATE_PARENT : 0;



	init.name = name;

	init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
@@ -216,7 +220,7 @@ struct clk *tegra_clk_register_periph(const char *name, 
		u32 offset, unsigned long flags)

{

	return _tegra_clk_register_periph(name, parent_names, num_parents,

			periph, clk_base, offset, true, flags);

			periph, clk_base, offset, flags);

}



struct clk *tegra_clk_register_periph_nodiv(const char *name,
@@ -224,6 +228,7 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name, 
		struct tegra_clk_periph *periph, void __iomem *clk_base,

		u32 offset)

{

	periph->gate.flags |= TEGRA_PERIPH_NO_DIV;

	return _tegra_clk_register_periph(name, parent_names, num_parents,

			periph, clk_base, offset, false, CLK_SET_RATE_PARENT);

			periph, clk_base, offset, CLK_SET_RATE_PARENT);

}

drivers/clk/tegra/clk.h

+1 −0
Original line number Diff line number Diff line
@@ -397,6 +397,7 @@ struct tegra_clk_periph_gate { 
#define TEGRA_PERIPH_MANUAL_RESET BIT(1)

#define TEGRA_PERIPH_ON_APB BIT(2)

#define TEGRA_PERIPH_WAR_1005168 BIT(3)

#define TEGRA_PERIPH_NO_DIV BIT(4)



void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);

extern const struct clk_ops tegra_clk_periph_gate_ops;