Commit 5e706c4d authored by Ankit Nautiyal's avatar Ankit Nautiyal Committed by Jani Nikula
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drm/edid: Split DSC parsing into separate function 



Move the DSC parsing logic into separate function.

v2: Rebase.

Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220916100551.2531750-3-ankit.k.nautiyal@intel.com
parent 18feaf6d

drivers/gpu/drm/drm_edid.c

+69 −59
Original line number Diff line number Diff line
@@ -5752,63 +5752,17 @@ static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 
	hdmi->y420_dc_modes = dc_mask;

}



/* Sink Capability Data Structure */

static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,

static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,

			       const u8 *hf_scds)

{

	struct drm_display_info *display = &connector->display_info;

	struct drm_hdmi_info *hdmi = &display->hdmi;



	display->has_hdmi_infoframe = true;



	if (hf_scds[6] & 0x80) {

		hdmi->scdc.supported = true;

		if (hf_scds[6] & 0x40)

			hdmi->scdc.read_request = true;

	}



	/*

	 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.

	 * And as per the spec, three factors confirm this:

	 * * Availability of a HF-VSDB block in EDID (check)

	 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)

	 * * SCDC support available (let's check)

	 * Lets check it out.

	 */



	if (hf_scds[5]) {

		/* max clock is 5000 KHz times block value */

		u32 max_tmds_clock = hf_scds[5] * 5000;

		struct drm_scdc *scdc = &hdmi->scdc;



		if (max_tmds_clock > 340000) {

			display->max_tmds_clock = max_tmds_clock;

			DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",

				display->max_tmds_clock);

		}



		if (scdc->supported) {

			scdc->scrambling.supported = true;



			/* Few sinks support scrambling for clocks < 340M */

			if ((hf_scds[6] & 0x8))

				scdc->scrambling.low_rates = true;

		}

	}



	if (hf_scds[7]) {

		u8 max_frl_rate;

		u8 dsc_max_frl_rate;

	u8 dsc_max_slices;

		struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;

	u8 dsc_max_frl_rate;



		DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");

		max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;

		drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,

				     &hdmi->max_frl_rate_per_lane);

	hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;



		if (hdmi_dsc->v_1p2) {

	if (!hdmi_dsc->v_1p2)

		return;



	hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;

	hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
@@ -5828,6 +5782,7 @@ static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 
	hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;



	dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;



	switch (dsc_max_slices) {

	case 1:

		hdmi_dsc->max_slices = 1;
@@ -5863,6 +5818,61 @@ static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 
		hdmi_dsc->clk_per_slice = 0;

	}

}



/* Sink Capability Data Structure */

static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,

				      const u8 *hf_scds)

{

	struct drm_display_info *display = &connector->display_info;

	struct drm_hdmi_info *hdmi = &display->hdmi;



	display->has_hdmi_infoframe = true;



	if (hf_scds[6] & 0x80) {

		hdmi->scdc.supported = true;

		if (hf_scds[6] & 0x40)

			hdmi->scdc.read_request = true;

	}



	/*

	 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.

	 * And as per the spec, three factors confirm this:

	 * * Availability of a HF-VSDB block in EDID (check)

	 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)

	 * * SCDC support available (let's check)

	 * Lets check it out.

	 */



	if (hf_scds[5]) {

		/* max clock is 5000 KHz times block value */

		u32 max_tmds_clock = hf_scds[5] * 5000;

		struct drm_scdc *scdc = &hdmi->scdc;



		if (max_tmds_clock > 340000) {

			display->max_tmds_clock = max_tmds_clock;

			DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",

				display->max_tmds_clock);

		}



		if (scdc->supported) {

			scdc->scrambling.supported = true;



			/* Few sinks support scrambling for clocks < 340M */

			if ((hf_scds[6] & 0x8))

				scdc->scrambling.low_rates = true;

		}

	}



	if (hf_scds[7]) {

		u8 max_frl_rate;

		struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;



		DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");

		max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;

		drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,

				     &hdmi->max_frl_rate_per_lane);



		drm_parse_dsc_info(hdmi_dsc, hf_scds);

	}



	drm_parse_ycbcr420_deep_color_info(connector, hf_scds);