Commit 5f11542f authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mvpp2-5gbase-r-support' 



Marek Behún says:

====================
Add 5gbase-r support for mvpp2

this adds support for 5gbase-r for mvpp2 driver. Current versions of
TF-A firmware support changing the PHY to 5gbase-r via SMC calls, at
least on Macchiatobin.

Tested on Macchiatobin.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 75e47206 4043ec70

drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

+37 −7
Original line number Diff line number Diff line
@@ -1488,6 +1488,7 @@ static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port) 
static bool mvpp2_is_xlg(phy_interface_t interface)

{

	return interface == PHY_INTERFACE_MODE_10GBASER ||

	       interface == PHY_INTERFACE_MODE_5GBASER ||

	       interface == PHY_INTERFACE_MODE_XAUI;

}
@@ -1627,6 +1628,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port, phy_interface_t interface) 
	case PHY_INTERFACE_MODE_2500BASEX:

		mvpp22_gop_init_sgmii(port);

		break;

	case PHY_INTERFACE_MODE_5GBASER:

	case PHY_INTERFACE_MODE_10GBASER:

		if (!mvpp2_port_supports_xlg(port))

			goto invalid_conf;
@@ -2186,6 +2188,7 @@ static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port, 
	xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);



	switch (interface) {

	case PHY_INTERFACE_MODE_5GBASER:

	case PHY_INTERFACE_MODE_10GBASER:

		val = readl(mpcs + MVPP22_MPCS_CLK_RESET);

		val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
@@ -6124,6 +6127,9 @@ static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs, 
	struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);

	u32 val;



	if (port->phy_interface == PHY_INTERFACE_MODE_5GBASER)

		state->speed = SPEED_5000;

	else

		state->speed = SPEED_10000;

	state->duplex = 1;

	state->an_complete = 1;
@@ -6877,10 +6883,34 @@ static int mvpp2_port_probe(struct platform_device *pdev, 
				MAC_SYM_PAUSE | MAC_ASYM_PAUSE;



		if (mvpp2_port_supports_xlg(port)) {

			/* If a COMPHY is present, we can support any of

			 * the serdes modes and switch between them.

			 */

			if (comphy) {

				__set_bit(PHY_INTERFACE_MODE_5GBASER,

					  port->phylink_config.supported_interfaces);

				__set_bit(PHY_INTERFACE_MODE_10GBASER,

					  port->phylink_config.supported_interfaces);

				__set_bit(PHY_INTERFACE_MODE_XAUI,

					  port->phylink_config.supported_interfaces);

			} else if (phy_mode == PHY_INTERFACE_MODE_5GBASER) {

				__set_bit(PHY_INTERFACE_MODE_5GBASER,

					  port->phylink_config.supported_interfaces);

			} else if (phy_mode == PHY_INTERFACE_MODE_10GBASER) {

				__set_bit(PHY_INTERFACE_MODE_10GBASER,

					  port->phylink_config.supported_interfaces);

			} else if (phy_mode == PHY_INTERFACE_MODE_XAUI) {

				__set_bit(PHY_INTERFACE_MODE_XAUI,

					  port->phylink_config.supported_interfaces);

			}



			if (comphy)

				port->phylink_config.mac_capabilities |=

					MAC_10000FD | MAC_5000FD;

			else if (phy_mode == PHY_INTERFACE_MODE_5GBASER)

				port->phylink_config.mac_capabilities |=

					MAC_5000FD;

			else

				port->phylink_config.mac_capabilities |=

					MAC_10000FD;

		}

drivers/phy/marvell/phy-mvebu-cp110-comphy.c

+9 −0
Original line number Diff line number Diff line
@@ -141,6 +141,7 @@ 
#define COMPHY_FW_SPEED_1250	0

#define COMPHY_FW_SPEED_3125	2

#define COMPHY_FW_SPEED_5000	3

#define COMPHY_FW_SPEED_515625	4

#define COMPHY_FW_SPEED_103125	6

#define COMPHY_FW_PORT_OFFSET	8

#define COMPHY_FW_PORT_MASK	GENMASK(11, 8)
@@ -220,6 +221,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = { 
	ETH_CONF(2, 0, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),

	ETH_CONF(2, 0, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_2500BASEX),

	ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, 0x1, COMPHY_FW_MODE_RXAUI),

	ETH_CONF(2, 0, PHY_INTERFACE_MODE_5GBASER, 0x1, COMPHY_FW_MODE_XFI),

	ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GBASER, 0x1, COMPHY_FW_MODE_XFI),

	GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),

	GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),
@@ -234,6 +236,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = { 
	/* lane 4 */

	ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),

	ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_2500BASEX),

	ETH_CONF(4, 0, PHY_INTERFACE_MODE_5GBASER, 0x2, COMPHY_FW_MODE_XFI),

	ETH_CONF(4, 0, PHY_INTERFACE_MODE_10GBASER, 0x2, COMPHY_FW_MODE_XFI),

	ETH_CONF(4, 0, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),

	GEN_CONF(4, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),
@@ -241,6 +244,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = { 
	GEN_CONF(4, 1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),

	ETH_CONF(4, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),

	ETH_CONF(4, 1, PHY_INTERFACE_MODE_2500BASEX, -1, COMPHY_FW_MODE_2500BASEX),

	ETH_CONF(4, 1, PHY_INTERFACE_MODE_5GBASER, -1, COMPHY_FW_MODE_XFI),

	ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GBASER, -1, COMPHY_FW_MODE_XFI),

	/* lane 5 */

	ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, 0x2, COMPHY_FW_MODE_RXAUI),
@@ -790,6 +794,11 @@ static int mvebu_comphy_power_on(struct phy *phy) 
				lane->id);

			fw_speed = COMPHY_FW_SPEED_3125;

			break;

		case PHY_INTERFACE_MODE_5GBASER:

			dev_dbg(priv->dev, "set lane %d to 5GBASE-R mode\n",

				lane->id);

			fw_speed = COMPHY_FW_SPEED_515625;

			break;

		case PHY_INTERFACE_MODE_10GBASER:

			dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",

				lane->id);