Commit 5f50d6b2 authored by Dan Williams's avatar Dan Williams
Browse files

cxl/mem: Move some definitions to mem.h 



In preparation for sharing cxl.h with other generic CXL consumers,
move / consolidate some of the memory device specifics to mem.h.

The motivation for moving out of cxl.h is to maintain least privilege
access to memory-device details since cxl.h is used in multiple files.
The motivation for moving definitions into a new mem.h header is for
code readability and organization. I.e. minimize implementation details
when reading data structures and other definitions.

Reviewed-by: default avatarBen Widawsky <ben.widawsky@intel.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/162096970932.1865304.14510894426562947262.stgit@dwillia2-desk3.amr.corp.intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 6efb943b

drivers/cxl/cxl.h

+0 −57
Original line number Diff line number Diff line
@@ -34,62 +34,5 @@ 
#define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18

#define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20



/* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */

#define CXLMDEV_STATUS_OFFSET 0x0

#define   CXLMDEV_DEV_FATAL BIT(0)

#define   CXLMDEV_FW_HALT BIT(1)

#define   CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)

#define     CXLMDEV_MS_NOT_READY 0

#define     CXLMDEV_MS_READY 1

#define     CXLMDEV_MS_ERROR 2

#define     CXLMDEV_MS_DISABLED 3

#define CXLMDEV_READY(status)                                                  \

	(FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) ==                \

	 CXLMDEV_MS_READY)

#define   CXLMDEV_MBOX_IF_READY BIT(4)

#define   CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)

#define     CXLMDEV_RESET_NEEDED_NOT 0

#define     CXLMDEV_RESET_NEEDED_COLD 1

#define     CXLMDEV_RESET_NEEDED_WARM 2

#define     CXLMDEV_RESET_NEEDED_HOT 3

#define     CXLMDEV_RESET_NEEDED_CXL 4

#define CXLMDEV_RESET_NEEDED(status)                                           \

	(FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) !=                       \

	 CXLMDEV_RESET_NEEDED_NOT)



struct cxl_memdev;

/**

 * struct cxl_mem - A CXL memory device

 * @pdev: The PCI device associated with this CXL device.

 * @regs: IO mappings to the device's MMIO

 * @status_regs: CXL 2.0 8.2.8.3 Device Status Registers

 * @mbox_regs: CXL 2.0 8.2.8.4 Mailbox Registers

 * @memdev_regs: CXL 2.0 8.2.8.5 Memory Device Registers

 * @payload_size: Size of space for payload

 *                (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)

 * @mbox_mutex: Mutex to synchronize mailbox access.

 * @firmware_version: Firmware version for the memory device.

 * @enabled_commands: Hardware commands found enabled in CEL.

 * @pmem_range: Persistent memory capacity information.

 * @ram_range: Volatile memory capacity information.

 */

struct cxl_mem {

	struct pci_dev *pdev;

	void __iomem *regs;

	struct cxl_memdev *cxlmd;



	void __iomem *status_regs;

	void __iomem *mbox_regs;

	void __iomem *memdev_regs;



	size_t payload_size;

	struct mutex mbox_mutex; /* Protects device mailbox and firmware */

	char firmware_version[0x10];

	unsigned long *enabled_cmds;



	struct range pmem_range;

	struct range ram_range;

};



extern struct bus_type cxl_bus_type;

#endif /* __CXL_H__ */

drivers/cxl/mem.c

+1 −20
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <linux/io-64-nonatomic-lo-hi.h>

#include "pci.h"

#include "cxl.h"

#include "mem.h"



/**

 * DOC: cxl mem
@@ -30,12 +31,6 @@ 
 *  - Handle and manage error conditions.

 */



/*

 * An entire PCI topology full of devices should be enough for any

 * config

 */

#define CXL_MEM_MAX_DEVS 65536



#define cxl_doorbell_busy(cxlm)                                                \

	(readl((cxlm)->mbox_regs + CXLDEV_MBOX_CTRL_OFFSET) &                  \

	 CXLDEV_MBOX_CTRL_DOORBELL)
@@ -92,20 +87,6 @@ struct mbox_cmd { 
#define CXL_MBOX_SUCCESS 0

};



/**

 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device

 * @dev: driver core device object

 * @cdev: char dev core object for ioctl operations

 * @cxlm: pointer to the parent device driver data

 * @id: id number of this memdev instance.

 */

struct cxl_memdev {

	struct device dev;

	struct cdev cdev;

	struct cxl_mem *cxlm;

	int id;

};



static int cxl_mem_major;

static DEFINE_IDA(cxl_memdev_ida);

static DECLARE_RWSEM(cxl_memdev_rwsem);

drivers/cxl/mem.h

0 → 100644
+81 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright(c) 2020-2021 Intel Corporation. */

#ifndef __CXL_MEM_H__

#define __CXL_MEM_H__



/* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */

#define CXLMDEV_STATUS_OFFSET 0x0

#define   CXLMDEV_DEV_FATAL BIT(0)

#define   CXLMDEV_FW_HALT BIT(1)

#define   CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)

#define     CXLMDEV_MS_NOT_READY 0

#define     CXLMDEV_MS_READY 1

#define     CXLMDEV_MS_ERROR 2

#define     CXLMDEV_MS_DISABLED 3

#define CXLMDEV_READY(status)                                                  \

	(FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) ==                \

	 CXLMDEV_MS_READY)

#define   CXLMDEV_MBOX_IF_READY BIT(4)

#define   CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)

#define     CXLMDEV_RESET_NEEDED_NOT 0

#define     CXLMDEV_RESET_NEEDED_COLD 1

#define     CXLMDEV_RESET_NEEDED_WARM 2

#define     CXLMDEV_RESET_NEEDED_HOT 3

#define     CXLMDEV_RESET_NEEDED_CXL 4

#define CXLMDEV_RESET_NEEDED(status)                                           \

	(FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) !=                       \

	 CXLMDEV_RESET_NEEDED_NOT)



/*

 * An entire PCI topology full of devices should be enough for any

 * config

 */

#define CXL_MEM_MAX_DEVS 65536



/**

 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device

 * @dev: driver core device object

 * @cdev: char dev core object for ioctl operations

 * @cxlm: pointer to the parent device driver data

 * @id: id number of this memdev instance.

 */

struct cxl_memdev {

	struct device dev;

	struct cdev cdev;

	struct cxl_mem *cxlm;

	int id;

};



/**

 * struct cxl_mem - A CXL memory device

 * @pdev: The PCI device associated with this CXL device.

 * @regs: IO mappings to the device's MMIO

 * @status_regs: CXL 2.0 8.2.8.3 Device Status Registers

 * @mbox_regs: CXL 2.0 8.2.8.4 Mailbox Registers

 * @memdev_regs: CXL 2.0 8.2.8.5 Memory Device Registers

 * @payload_size: Size of space for payload

 *                (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)

 * @mbox_mutex: Mutex to synchronize mailbox access.

 * @firmware_version: Firmware version for the memory device.

 * @enabled_cmds: Hardware commands found enabled in CEL.

 * @pmem_range: Persistent memory capacity information.

 * @ram_range: Volatile memory capacity information.

 */

struct cxl_mem {

	struct pci_dev *pdev;

	void __iomem *regs;

	struct cxl_memdev *cxlmd;



	void __iomem *status_regs;

	void __iomem *mbox_regs;

	void __iomem *memdev_regs;



	size_t payload_size;

	struct mutex mbox_mutex; /* Protects device mailbox and firmware */

	char firmware_version[0x10];

	unsigned long *enabled_cmds;



	struct range pmem_range;

	struct range ram_range;

};

#endif /* __CXL_MEM_H__ */