Commit 5f88a93b authored by Chunfeng Yun's avatar Chunfeng Yun Committed by Vinod Koul
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phy: mediatek: mipi: mt8183: use common helper to access registers 



Use MediaTek phy's common helper to access registers, then we can remove
mipi-dsi's I/O helpers.

Signed-off-by: default avatarChunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220920090038.15133-18-chunfeng.yun@mediatek.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent d36d69a5

drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c

+34 −34
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 * Author: jitao.shi <jitao.shi@mediatek.com>

 */



#include "phy-mtk-io.h"

#include "phy-mtk-mipi-dsi.h"



#define MIPITX_LANE_CON		0x000c
@@ -46,6 +47,7 @@ 
static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)

{

	struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);

	void __iomem *base = mipi_tx->regs;

	unsigned int txdiv, txdiv0;

	u64 pcw;
@@ -70,17 +72,16 @@ static int mtk_mipi_tx_pll_enable(struct clk_hw *hw) 
		return -EINVAL;

	}



	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);

	mtk_phy_clear_bits(base + MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);



	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);

	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);

	mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);

	mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);

	udelay(1);

	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);

	mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);

	pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000);

	writel(pcw, mipi_tx->regs + MIPITX_PLL_CON0);

	mtk_mipi_tx_update_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV,

				txdiv0 << 8);

	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);

	writel(pcw, base + MIPITX_PLL_CON0);

	mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0);

	mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);



	return 0;

}
@@ -88,11 +89,12 @@ static int mtk_mipi_tx_pll_enable(struct clk_hw *hw) 
static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)

{

	struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);

	void __iomem *base = mipi_tx->regs;



	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);

	mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);



	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);

	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);

	mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);

	mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);

}



static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -121,7 +123,7 @@ static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) 
			mipi_tx->rt_code[i] |= 0x10 << 5;



		for (j = 0; j < 10; j++)

			mtk_mipi_tx_update_bits(mipi_tx,

			mtk_phy_update_bits(mipi_tx->regs +

				MIPITX_D2P_RTCODE * (i + 1) + j * 4,

				1, mipi_tx->rt_code[i] >> j & 1);

	}
@@ -130,44 +132,42 @@ static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) 
static void mtk_mipi_tx_power_on_signal(struct phy *phy)

{

	struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);

	void __iomem *base = mipi_tx->regs;



	/* BG_LPF_EN / BG_CORE_EN */

	writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN,

	       mipi_tx->regs + MIPITX_LANE_CON);

	writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);

	usleep_range(30, 100);

	writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN,

	       mipi_tx->regs + MIPITX_LANE_CON);

	writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN, base + MIPITX_LANE_CON);



	/* Switch OFF each Lane */

	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_phy_clear_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);



	mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL,

				RG_DSI_HSTX_LDO_REF_SEL,

				(mipi_tx->mipitx_drive - 3000) / 200 << 6);

	mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_HSTX_LDO_REF_SEL,

			     (mipi_tx->mipitx_drive - 3000) / 200);



	mtk_mipi_tx_config_calibration_data(mipi_tx);



	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);

	mtk_phy_set_bits(base + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);

}



static void mtk_mipi_tx_power_off_signal(struct phy *phy)

{

	struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);

	void __iomem *base = mipi_tx->regs;



	/* Switch ON each Lane */

	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);



	writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN,

	       mipi_tx->regs + MIPITX_LANE_CON);

	writel(RG_DSI_PAD_TIEL_SEL, mipi_tx->regs + MIPITX_LANE_CON);

	mtk_phy_set_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_phy_set_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_phy_set_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_phy_set_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);

	mtk_phy_set_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);



	writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);

	writel(RG_DSI_PAD_TIEL_SEL, base + MIPITX_LANE_CON);

}



const struct mtk_mipitx_data mt8183_mipitx_data = {