Commit 5fba65ef authored by Radhakrishna Sripada's avatar Radhakrishna Sripada Committed by Matt Roper
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drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203 



Both workarounds require the same implementation and apply to MTL P and
M from stepping A0 to B0 (exclusive).

v2:
  - Remove unrelated brace removal. (Matt)

Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230329212336.106161-2-gustavo.sousa@intel.com
parent 49f6f648

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -1146,6 +1146,7 @@ 
#define   ENABLE_SMALLPL			REG_BIT(15)

#define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)

#define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)

#define   MTL_DISABLE_SAMPLER_SC_OOO		REG_BIT(3)



#define GEN9_HALF_SLICE_CHICKEN7		MCR_REG(0xe194)

#define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+9 −0
Original line number Diff line number Diff line
@@ -3051,6 +3051,15 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li 


	add_render_compute_tuning_settings(i915, wal);



	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||

	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))

		/*

		 * Wa_14017066071

		 * Wa_14017654203

		 */

		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,

				 MTL_DISABLE_SAMPLER_SC_OOO);



	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||

	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||

	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||