Commit 5fc11598 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: expand dml structs 



Add more fields to support upcoming dml versions

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 09178aaa

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+32 −3
Original line number Diff line number Diff line
@@ -1858,6 +1858,22 @@ void dcn20_populate_dml_writeback_from_context( 


}



static int get_num_odm_heads(struct pipe_ctx *pipe)

{

	int odm_head_count = 0;

	struct pipe_ctx *next_pipe = pipe->next_odm_pipe;

	while (next_pipe) {

		odm_head_count++;

		next_pipe = next_pipe->next_odm_pipe;

	}

	pipe = pipe->prev_odm_pipe;

	while (pipe) {

		odm_head_count++;

		pipe = pipe->prev_odm_pipe;

	}

	return odm_head_count ? odm_head_count + 1 : 0;

}



int dcn20_populate_dml_pipes_from_context(

		struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)

{
@@ -1897,6 +1913,8 @@ int dcn20_populate_dml_pipes_from_context( 
		pipes[pipe_cnt].pipe.src.dcc = 0;

		pipes[pipe_cnt].pipe.src.vm = 0;*/



		pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;



		pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;

		/* todo: rotation?*/

		pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
@@ -1935,8 +1953,13 @@ int dcn20_populate_dml_pipes_from_context( 
		pipes[pipe_cnt].dout.dp_lanes = 4;

		pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;

		pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;

		pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe

							|| res_ctx->pipe_ctx[i].next_odm_pipe;

		switch (get_num_odm_heads(&res_ctx->pipe_ctx[i])) {

		case 2:

			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;

			break;

		default:

			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;

		}

		pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;

		if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state

				== res_ctx->pipe_ctx[i].plane_state)
@@ -2046,6 +2069,9 @@ int dcn20_populate_dml_pipes_from_context( 
			if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)

				pipes[pipe_cnt].pipe.src.viewport_height = 1080;

			pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;

			pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;

			pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;

			pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;

			pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */

			pipes[pipe_cnt].pipe.src.source_format = dm_444_32;

			pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
@@ -2079,7 +2105,10 @@ int dcn20_populate_dml_pipes_from_context( 
			pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;

			pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;

			pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;

			pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;

			pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;

			pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;

			pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;

			if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {

				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;

				pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
@@ -2493,7 +2522,7 @@ int dcn20_validate_apply_pipe_split_flags( 
			split[i] = true;

		if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {

			split[i] = true;

			context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true;

			context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = dm_odm_combine_mode_2to1;

		}

		context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] =

			context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

+82 −83

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

+83 −84

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c

+78 −79

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h

+16 −0
Original line number Diff line number Diff line
@@ -119,6 +119,10 @@ enum mpc_combine_affinity { 
	dm_mpc_never

};



enum RequestType {

	REQ_256Bytes, REQ_128BytesNonContiguous, REQ_128BytesContiguous, REQ_NA

};



enum self_refresh_affinity {

	dm_try_to_allow_self_refresh_and_mclk_switch,

	dm_allow_self_refresh_and_mclk_switch,
@@ -165,4 +169,16 @@ enum odm_combine_mode { 
	dm_odm_combine_mode_4to1,

};



enum odm_combine_policy {

	dm_odm_combine_policy_dal,

	dm_odm_combine_policy_none,

	dm_odm_combine_policy_2to1,

	dm_odm_combine_policy_4to1,

};



enum immediate_flip_requirement {

	dm_immediate_flip_not_required,

	dm_immediate_flip_required,

};



#endif