Commit 5fc21d1b authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
Browse files

phy: qcom-qmp: split allegedly 4.20 and 5.20 TX/RX registers 



Split registers definitions belonging allegedly to 4.20 and 5.20 QMP
PHYs. They are used for the PCIe QMP PHYs, which have no good open
source reference.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-19-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 87d71378

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4_20.h

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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 */



#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_

#define QCOM_PHY_QMP_QSERDES_TXRX_V4_20_H_



/* Only for QMP V4_20 PHY - TX registers */

#define QSERDES_V4_20_TX_LANE_MODE_1			0x88

#define QSERDES_V4_20_TX_LANE_MODE_2			0x8c

#define QSERDES_V4_20_TX_LANE_MODE_3			0x90

#define QSERDES_V4_20_TX_VMODE_CTRL1			0xc4

#define QSERDES_V4_20_TX_PI_QEC_CTRL			0xe0



/* Only for QMP V4_20 PHY - RX registers */

#define QSERDES_V4_20_RX_FO_GAIN_RATE2			0x008

#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS		0x058

#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE		0x0ac

#define QSERDES_V4_20_RX_DFE_3				0x110

#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1		0x134

#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2		0x138

#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2			0x150

#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x178

#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1		0x1c8

#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2		0x1cc

#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3		0x1d0

#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4		0x1d4

#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0		0x1d8

#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1		0x1dc

#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2		0x1e0

#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3		0x1e4

#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4		0x1e8

#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0		0x1ec

#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1		0x1f0

#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2		0x1f4

#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3		0x1f8

#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4		0x1fc

#define QSERDES_V4_20_RX_PHPRE_CTRL			0x200

#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET	0x20c

#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2		0x23c



#endif

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h

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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 */



#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_

#define QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_



/* Only for QMP V5_20 PHY - TX registers */

#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX	0x30

#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX	0x34

#define QSERDES_V5_20_TX_LANE_MODE_1			0x78

#define QSERDES_V5_20_TX_LANE_MODE_2			0x7c



/* Only for QMP V5_20 PHY - RX registers */

#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2		0x008

#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3		0x00c

#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS		0x020

#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1	0x02c

#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3	0x030

#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET		0x07c

#define QSERDES_V5_20_RX_DFE_3				0x090

#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1		0x0b4

#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1		0x0c4

#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2		0x0c8

#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL		0x0dc

#define QSERDES_V5_20_RX_GM_CAL				0x0ec

#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4		0x108

#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1		0x164

#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2		0x168

#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3		0x16c

#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5		0x174

#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6		0x178

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0		0x17c

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1		0x180

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2		0x184

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3		0x188

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4		0x18c

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5		0x190

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6		0x194

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0		0x198

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1		0x19c

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2		0x1a0

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3		0x1a4

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4		0x1a8

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5		0x1ac

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6		0x1b0

#define QSERDES_V5_20_RX_PHPRE_CTRL			0x1b4

#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET	0x1c0

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210	0x1f4

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3	0x1f8

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210	0x1fc

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3	0x200

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210	0x204

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3	0x208

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3	0x210

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3	0x218

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3	0x220



#endif

drivers/phy/qualcomm/phy-qcom-qmp.h

+2 −86
Original line number Diff line number Diff line
@@ -14,9 +14,11 @@ 


#include "phy-qcom-qmp-qserdes-com-v4.h"

#include "phy-qcom-qmp-qserdes-txrx-v4.h"

#include "phy-qcom-qmp-qserdes-txrx-v4_20.h"



#include "phy-qcom-qmp-qserdes-com-v5.h"

#include "phy-qcom-qmp-qserdes-txrx-v5.h"

#include "phy-qcom-qmp-qserdes-txrx-v5_20.h"



#include "phy-qcom-qmp-qserdes-pll.h"
@@ -108,14 +110,6 @@ 


#define QSERDES_V3_DP_PHY_STATUS			0x0c0





/* Only for QMP V4_20 PHY - TX registers */

#define QSERDES_V4_20_TX_LANE_MODE_1			0x88

#define QSERDES_V4_20_TX_LANE_MODE_2			0x8c

#define QSERDES_V4_20_TX_LANE_MODE_3			0x90

#define QSERDES_V4_20_TX_VMODE_CTRL1			0xc4

#define QSERDES_V4_20_TX_PI_QEC_CTRL			0xe0



/* Only for QMP V4 PHY - DP PHY registers */

#define QSERDES_V4_DP_PHY_CFG_1				0x014

#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK		0x054
@@ -127,33 +121,6 @@ 
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS		0x0d8

#define QSERDES_V4_DP_PHY_STATUS			0x0dc



/* Only for QMP V4_20 PHY - RX registers */

#define QSERDES_V4_20_RX_FO_GAIN_RATE2			0x008

#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS		0x058

#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE		0x0ac

#define QSERDES_V4_20_RX_DFE_3				0x110

#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1		0x134

#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2		0x138

#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2			0x150

#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x178

#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1		0x1c8

#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2		0x1cc

#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3		0x1d0

#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4		0x1d4

#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0		0x1d8

#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1		0x1dc

#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2		0x1e0

#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3		0x1e4

#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4		0x1e8

#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0		0x1ec

#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1		0x1f0

#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2		0x1f4

#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3		0x1f8

#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4		0x1fc

#define QSERDES_V4_20_RX_PHPRE_CTRL			0x200

#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET	0x20c

#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2		0x23c



/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */

#define QPHY_V4_20_PCS_RX_SIGDET_LVL			0x188

#define QPHY_V4_20_PCS_EQ_CONFIG2			0x1d8
@@ -176,57 +143,6 @@ 
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2		0x824

#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2		0x828



/* Only for QMP V5_20 PHY - TX registers */

#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX	0x30

#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX	0x34

#define QSERDES_V5_20_TX_LANE_MODE_1			0x78

#define QSERDES_V5_20_TX_LANE_MODE_2			0x7c



/* Only for QMP V5_20 PHY - RX registers */

#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2		0x008

#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3		0x00c

#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS		0x020

#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1	0x02c

#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3	0x030

#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET		0x07c

#define QSERDES_V5_20_RX_DFE_3				0x090

#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1		0x0b4

#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1		0x0c4

#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2		0x0c8

#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL		0x0dc

#define QSERDES_V5_20_RX_GM_CAL				0x0ec

#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4		0x108

#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1		0x164

#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2		0x168

#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3		0x16c

#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5		0x174

#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6		0x178

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0		0x17c

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1		0x180

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2		0x184

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3		0x188

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4		0x18c

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5		0x190

#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6		0x194

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0		0x198

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1		0x19c

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2		0x1a0

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3		0x1a4

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4		0x1a8

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5		0x1ac

#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6		0x1b0

#define QSERDES_V5_20_RX_PHPRE_CTRL			0x1b4

#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET	0x1c0

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210	0x1f4

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3	0x1f8

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210	0x1fc

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3	0x200

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210	0x204

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3	0x208

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3	0x210

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3	0x218

#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3	0x220



/* Only for QMP V5_20 PHY - PCIe PCS registers */

#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE	0x01c

#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS		0x090